As Mark pointed out, the driver should register all regulators
regardless of how many are used in the system in order to aid diagnostics.
But in the previous patch, only register the regulators that are used.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
There is no need to jump to the 'err' label.
Returnn the error directly instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Provide a MODULE_ALIAS() entry to the driver.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Due to the following commit
commit 160a061301
Author: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Date: Mon Nov 11 14:13:41 2013 +0800
spi/qspi: set correct platform drvdata in ti_qspi_probe()
The ti_qspi_remove() use the platform drvdata as a type of
struct ti_qspi, we should pass correct platform drvdata to
platform_set_drvdata() in ti_qspi_probe().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mark Brown <broonie@linaro.org>
platform_set_drvdata was changed in the probe, so we need to
correspondingly change deferencing of qspi in runtime resume
path. Else, this will lead to a NULL dereference pointer.
Based on v3.13-rc3
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The changes in the ACPI-based PCI hotplug (ACPIPHP) subsystem made
during the 3.12 development cycle uncovered a problem with VGA
switcheroo that on some systems, when the device-specific method
(ATPX in the radeon case, _DSM in the nouveau case) is used to turn
off the discrete graphics, the BIOS generates ACPI hotplug events for
that device and those events cause ACPIPHP to attempt to remove the
device from the system (they are events for a device that was present
previously and is not present any more, so that's what should be done
according to the spec). Then, the system stops functioning correctly.
Since the hotplug events in question were simply silently ignored
previously, the least intrusive way to address that problem is to
make ACPIPHP ignore them again. For this purpose, introduce a new
ACPI device flag, no_hotplug, and modify ACPIPHP to ignore hotplug
events for PCI devices whose ACPI companions have that flag set.
Next, make the radeon and nouveau switcheroo detection code set the
no_hotplug flag for the discrete graphics' ACPI companion.
Fixes: bbd34fcdd1 (ACPI / hotplug / PCI: Register all devices under the given bridge)
References: https://bugzilla.kernel.org/show_bug.cgi?id=61891
References: https://bugzilla.kernel.org/show_bug.cgi?id=64891
Reported-and-tested-by: Mike Lothian <mike@fireburn.co.uk>
Reported-and-tested-by: <madcatx@atlas.cz>
Reported-and-tested-by: Joaquín Aramendía <samsagax@gmail.com>
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Dave Airlie <airlied@linux.ie>
Cc: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: 3.12+ <stable@vger.kernel.org> # 3.12+
Migrate mmio code and core driver to managed resources to reduce boilerplate
error handling code. Also, handle clk_enable() failure while at it, and drop
unused dw_spi iolen field.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Mark Brown <broonie@linaro.org>
When call snd_soc_register_card, it will set driver data to this
device through dev_set_drvdata, then in driver, no need to call
platform_set_drvdata again, so remove it.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch adds support for the PCI ID provided by the Marvell 88SE9170
SATA controller.
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: stable@vger.kernel.org
Revert the SAI's endianess for fifo data to/from DMA engine.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This is maybe one bug or a limitation of the hardware that the {T,R}CR2's
Synchronous Mode bits must be set as late as possible, or the SAI device
maybe hanged up, and there has not any explaination about this limitation
in the SAI Data Sheet.
And the {T,R}CR2's Synchronous Mode bits must be set at the same time whether
for Tx or Rx stream.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
It seems commit d764593a "crypto: aesni - AVX and AVX2 version of AESNI-GCM
encode and decode" breaks a build on x86_32 since it's designed only for
x86_64. This patch makes a compilation unit conditional to CONFIG_64BIT and
functions usage to CONFIG_X86_64.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
plat/regs-ata.h is used only by Samsung PATA driver.
Move this file to the drivers folder to remove platform
dependency required for multiplatform support.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
The bond 3ad and TLB/ALB has the same check path, so combine them.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The bond driver could set the lp_interval when loading module.
Suggested-by: Scott Feldman <sfeldma@cumulusnetworks.com>
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Improve the comment of SW workaround for CCM lpm issue using
hardware errata description to avoid confusion.
ERR007265: CCM: When improper low-power sequence is used, the SoC
enters low power mode before the ARM core executes WFI.
Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending
by setting IOMUX_GPR1_GINT.
2) Software should then unmask IRQ #32 in GPC before setting CCM
Low-Power mode.
3) Software should mask IRQ #32 right after CCM Low-Power mode is
set (set bits 0-1 of CCM_CLPCR).
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.
2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.
PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
PFUZE100 regulator is commonly found on mx6 based designs.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Let MX35 and MX50 device tree support be built by default.
Generated by doing:
- Selected CONFIG_MACH_IMX35_DT and CONFIG_SOC_IMX50 via 'make menuconfig'
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Update the IMX v6/v7 defconfig for the SolidRun HummingBoard:
- Add AT803X ethernet phy
- Add consumer IR devices
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We are missing spba clock in imx6sl's clock tree, thus add it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
0-DAY kernel build testing backend reports the following.
scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
# many are suggestions rather than must-fix
ERROR: Use of const init definition must use __initconst
#80: arch/arm/mach-imx/mach-imx50.c:26:
+static const char *imx50_dt_board_compat[] __initdata = {
While at it, fix the error globally for IMX platform.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.
In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.
This patch fixes this issue.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.
While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since the RTNL can't always be held, use wdev/sdata locking for
the qos-map dereference in mac80211. This requires cfg80211 to
consistently lock it, which it was missing in one place.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Update arch.apic_base before triggering recalculate_apic_map. Otherwise
the recalculation will work against the previous state of the APIC and
will fail to build the correct map when an APIC is hardware-enabled
again.
This fixes a regression of 1e08ec4a13.
Cc: stable@vger.kernel.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
