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915,380 commits

Author SHA1 Message Date
Stephen Boyd
3a57530b7d Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next
- Allow the COMMON_CLK config to be selectable

* clk-selectable:
  clk: Move HAVE_CLK config out of architecture layer
  MIPS: Loongson64: Drop asm/clock.h include
  ARM: mmp: Remove legacy clk code
  clk: Allow the common clk framework to be selectable
  mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
  MIPS: Remove redundant CLKDEV_LOOKUP selects
  h8300: Remove redundant CLKDEV_LOOKUP selects
  arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
  ARM: Remove redundant CLKDEV_LOOKUP selects
  ARM: Remove redundant COMMON_CLK selects

* clk-amlogic:
  clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
  clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
  clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
  clk: meson: meson8b: Fix the polarity of the RESET_N lines
  clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
  clk: meson: g12a: Prepare the GPU clock tree to change at runtime
  clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
  clk: meson: meson8b: make the hdmi_sys clock tree mutable
  clk: meson8b: export the HDMI system clock

* clk-renesas:
  dt-bindings: clock: renesas: mstp: Convert to json-schema
  dt-bindings: clock: renesas: div6: Convert to json-schema
  clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
  clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
  clk: renesas: cpg-mssr: Add R8A7742 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
  MAINTAINERS: Add DT Bindings for Renesas Clock Generators
  clk: renesas: r9a06g032: Fix some typo in comments
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support

* clk-samsung:
  clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
  ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
  clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
  clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical

* clk-allwinner:
  clk: sunxi: Fix incorrect usage of round_down()
2020-06-01 12:59:46 -07:00
Stephen Boyd
33b52f7cc9 This time we only have a single minor rounding fix for the legacy
Allwinner clock support.
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Merge tag 'sunxi-clk-for-5.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull an Allwinner clk driver fix from Maxime Ripard:

 - a single minor rounding fix for the legacy Allwinner clock support

* tag 'sunxi-clk-for-5.8-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi: Fix incorrect usage of round_down()
2020-05-21 15:47:37 -07:00
Stephen Boyd
fe95d2e92e clk/samsung updates for 5.8
- Regression fixes for exynos542x and exynos5433 SoCs,
  - use of fallthrough; attribute for s3c24xx.
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Merge tag 'clk-v5.8-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - Regression fixes for exynos542x and exynos5433 SoCs
 - use of fallthrough; attribute for s3c24xx

* tag 'clk-v5.8-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
  ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
  clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
  clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
2020-05-21 15:43:32 -07:00
Stephen Boyd
571a6b4755 clk: renesas: Updates for v5.8 (take two)
- A minor fix for the currently unused suspend/resume handling on
     RZ/A1 and RZ/A2,
   - Two more conversions of DT bindings to json-schema.
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Merge tag 'clk-renesas-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - A minor fix for the currently unused suspend/resume handling on
    RZ/A1 and RZ/A2
  - Two more conversions of Renesas DT bindings to json-schema

* tag 'clk-renesas-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas: mstp: Convert to json-schema
  dt-bindings: clock: renesas: div6: Convert to json-schema
  clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
2020-05-21 15:37:54 -07:00
Geert Uytterhoeven
9b9df63b50 dt-bindings: clock: renesas: mstp: Convert to json-schema
Convert the Renesas Clock Pulse Generator (CPG) Module Stop (MSTP)
Clocks Device Tree binding documentation to json-schema.

Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Replace the obsolete example for R-Car H2 by an example that is still
valid.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200508100321.6720-1-geert+renesas@glider.be
2020-05-20 14:08:15 +02:00
Marek Szyprowski
25bdae0f1c clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
Mark the SCLK clock for Exynos5433 I2S1 device with IGNORE_UNUSED flag to
match its behaviour with SCLK clock for AUD_I2S (I2S0) device until
a proper fix for Exynos I2S driver is ready.

This fixes the following synchronous abort issue revealed by the probe
order change caused by the commit 93d2e4322a ("of: platform: Batch
fwnode parsing when adding all top level devices")

Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 50 Comm: kworker/0:1 Not tainted 5.7.0-rc5+ #701
Hardware name: Samsung TM2E board (DT)
Workqueue: events deferred_probe_work_func
pstate: 60000005 (nZCv daif -PAN -UAO)
pc : samsung_i2s_probe+0x768/0x8f0
lr : samsung_i2s_probe+0x688/0x8f0
...
Call trace:
 samsung_i2s_probe+0x768/0x8f0
 platform_drv_probe+0x50/0xa8
 really_probe+0x108/0x370
 driver_probe_device+0x54/0xb8
 __device_attach_driver+0x90/0xc0
 bus_for_each_drv+0x70/0xc8
 __device_attach+0xdc/0x140
 device_initial_probe+0x10/0x18
 bus_probe_device+0x94/0xa0
 deferred_probe_work_func+0x70/0xa8
 process_one_work+0x2a8/0x718
 worker_thread+0x48/0x470
 kthread+0x134/0x160
 ret_from_fork+0x10/0x1c
Code: 17ffffaf d503201f f94086c0 91003000 (88dffc00)
---[ end trace ccf721c9400ddbd6 ]---

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-05-19 16:58:42 +02:00
Joe Perches
81eeae43c3 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
Convert the various uses of fallthrough comments to fallthrough;

Done via script
Link: https://lore.kernel.org/lkml/b56602fcf79f849e733e7b521bb0e17895d390fa.1582230379.git.joe@perches.com/

Signed-off-by: Joe Perches <joe@perches.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de> # for the I2C part
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-05-19 16:58:42 +02:00
Geert Uytterhoeven
59e7166fe0 dt-bindings: clock: renesas: div6: Convert to json-schema
Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
json-schema.

Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Update the example to match reality.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200507075026.31941-1-geert+renesas@glider.be
2020-05-18 11:07:23 +02:00
Geert Uytterhoeven
ace3420977 clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
On SoCs with Standby Control Registers (STBCRs) instead of Module Stop
Control Registers (MSTPCRs), the suspend handler saves the wrong
registers, and the resume handler prints the wrong register in an error
message.

Fortunately this cannot happen yet, as the suspend/resume code is used
on PSCI systems only, and systems with STBCRs (RZ/A1 and RZ/A2) do not
use PSCI.  Still, it is better to fix this, to avoid this becoming a
problem in the future.

Distinguish between STBCRs and MSTPCRs where needed.  Replace the
useless printing of the virtual register address in the resume error
message by printing the register index.

Fixes: fde35c9c7d ("clk: renesas: cpg-mssr: Add R7S9210 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200507074713.30113-1-geert+renesas@glider.be
2020-05-18 11:06:33 +02:00
Stephen Boyd
07fbf0e58d Amlogic clock updates for v5.8:
* Meson8b: Updates and fixup HDMI and video clocks
 * Meson8b: Fixup reset polarity
 * Meson gx and g12: fix GPU glitch free mux switch
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Merge tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

- Meson8b: Updates and fixup HDMI and video clocks
- Meson8b: Fixup reset polarity
- Meson gx and g12: fix GPU glitch free mux switch

* tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
  clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
  clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
  clk: meson: meson8b: Fix the polarity of the RESET_N lines
  clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
  clk: meson: g12a: Prepare the GPU clock tree to change at runtime
  clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
  clk: meson: meson8b: make the hdmi_sys clock tree mutable
  clk: meson8b: export the HDMI system clock
2020-05-14 13:37:51 -07:00
Marek Szyprowski
4b159cf13a clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
The proper name for CLK_SMMU_FIMCL3 is "smmu_fimcl3". Remove obvious
typo.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-05-13 12:42:15 +02:00
Marek Szyprowski
e47bd937e6 clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
The TOP 'aclk*_isp', 'aclk550_cam', 'gscl_wa' and 'gscl_wb' clocks must
be kept enabled all the time to allow proper access to power management
control for the ISP and CAM power domains. The last two clocks, although
related to GScaler device and GSCL power domain, provides also the
I_WRAP_CLK signal to MIPI CSIS0/1 devices, which are a part of CAM power
domain and are needed for proper power on/off sequence.

Currently there are no drivers for the devices, which are part of CAM and
ISP power domains yet. This patch only fixes the race between disabling
the unused power domains and disabling unused clocks, which randomly
resulted in the following error during boot:

Power domain CAM disable failed
Power domain ISP disable failed

Fixes: 318fa46cc6 ("clk/samsung: exynos542x: mark some clocks as critical")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-05-13 12:40:50 +02:00
Stephen Boyd
bc8c945e0a clk: Move HAVE_CLK config out of architecture layer
The implementation of 'struct clk' is not really an architectual detail
anymore now that most architectures have migrated to the common clk
framework. To sway new architecture ports away from trying to implement
their own 'struct clk', move the config next to the common clk framework
config.

Cc: Russell King <linux@armlinux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-11-sboyd@kernel.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-12 20:28:03 -07:00
Stephen Boyd
c7725c9b74 MIPS: Loongson64: Drop asm/clock.h include
This include isn't used by this file, so just remove it.

Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: <linux-mips@vger.kernel.org>
Cc: <chenhc@lemote.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-10-sboyd@kernel.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-12 20:28:03 -07:00
Stephen Boyd
3819ad4402 ARM: mmp: Remove legacy clk code
Remove all the legacy clk code that supports a non-common clk framework
implementation of 'struct clk' in mach-mmp. This code doesn't look to be
compiled anymore given that the MMP is fully supported in the
multi-platform config via ARCH_MULTIPLATFORM as of commit 377524dc4d
("ARM: mmp: move into ARCH_MULTIPLATFORM"). The ARCH_MULTIPLATFORM
config selects COMMON_CLK and therefore the Makefile rule can never
actually compile the code in these files.

Cc: Lubomir Rintel <lkundrak@v3.sk>
Cc: Russell King <linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-9-sboyd@kernel.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
[sboyd@kernel.org: Squash in a clock.h include removal found by Stephen
Rothwell <sfr@canb.auug.org.au>]
2020-05-12 20:28:03 -07:00
Stephen Boyd
bbd7ffdbef clk: Allow the common clk framework to be selectable
Enable build testing and configuration control of the common clk
framework so that more code coverage and testing can be done on the
common clk framework across various architectures. This also nicely
removes the requirement that architectures must select the framework
when they don't use it in architecture code.

There's one snag with doing this, and that's making sure that randconfig
builds don't select this option when some architecture or platform
implements 'struct clk' outside of the common clk framework. Introduce a
new config option 'HAVE_LEGACY_CLK' to indicate those platforms that
haven't migrated to the common clk framework and therefore shouldn't be
allowed to select this new config option. Also add a note that we hope
one day to remove this config entirely.

Based on a patch by Mark Brown <broonie@kernel.org>.

Cc: Mark Brown <broonie@kernel.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Mark Salter <msalter@redhat.com>
Cc: Aurelien Jacquiot <jacquiot.aurelien@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Rich Felker <dalias@libc.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: <linux-mips@vger.kernel.org>
Cc: <linux-c6x-dev@linux-c6x.org>
Cc: <linux-m68k@lists.linux-m68k.org>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: <linux-sh@vger.kernel.org>
Link: https://lore.kernel.org/r/1470915049-15249-1-git-send-email-broonie@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-8-sboyd@kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-05 12:34:11 -07:00
Stephen Boyd
3fd2fdb311 mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
Making COMMON_CLK a visible option causes the sparc allyesconfig to fail
to build like so:

   sparc64-linux-ld: drivers/mmc/host/meson-mx-sdio.o: in function `meson_mx_mmc_remove':
   meson-mx-sdio.c:(.text+0x70): undefined reference to `of_platform_device_destroy'
   sparc64-linux-ld: drivers/mmc/host/meson-mx-sdio.o: in function `meson_mx_mmc_probe':
   meson-mx-sdio.c:(.text+0x9e4): undefined reference to `of_platform_device_create'
   sparc64-linux-ld: meson-mx-sdio.c:(.text+0xdd4): undefined reference to `of_platform_device_destroy'

This is because the implementation of of_platform_device_destroy() is
inside an #ifdef CONFIG_OF_ADDRESS section of drivers/of/platform.c.
This driver already depends on OF being enabled, so let's tighten that
constrain a little more so that it depends on OF_ADDRESS instead. This
way we won't try to build this driver on platforms that don't have this
function.

Reported-by: kbuild test robot <lkp@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200409064416.83340-7-sboyd@kernel.org
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-05 12:34:06 -07:00
Stephen Boyd
b62bc0474b MIPS: Remove redundant CLKDEV_LOOKUP selects
The ATH79 config selects COMMON_CLK already, and the COMMON_CLK config
option already selects CLKDEV_LOOKUP, and CLKDEV_LOOKUP already selects
HAVE_CLK so it's redundant to have these selected again.

Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: <linux-mips@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200409064416.83340-6-sboyd@kernel.org
2020-05-05 12:34:04 -07:00
Stephen Boyd
ba76c40dbe h8300: Remove redundant CLKDEV_LOOKUP selects
The h8300 architecture selects COMMON_CLK already, and the COMMON_CLK
config option already selects CLKDEV_LOOKUP so it's redundant to have
this selected again.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: uclinux-h8-devel@lists.sourceforge.jp
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200409064416.83340-5-sboyd@kernel.org
2020-05-05 12:34:01 -07:00
Stephen Boyd
d823836ad1 arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
The arm64 architecture selects COMMON_CLK at the toplevel ARM64 config.
The COMMON_CLK config option already selects CLKDEV_LOOKUP so it's
redundant to have this selected again for the Tegra specific config.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200409064416.83340-4-sboyd@kernel.org
2020-05-05 12:33:59 -07:00
Stephen Boyd
e8bd633bc0 ARM: Remove redundant CLKDEV_LOOKUP selects
These platforms select COMMON_CLK indirectly through use of the
ARCH_MULTIPLATFORM config option that they depend on implicitly via some
V7/V6/V5 multi platform config option. The COMMON_CLK config option
already selects CLKDEV_LOOKUP so it's redundant to have this selected
again.

Cc: Tony Prisk <linux@prisktech.co.nz>
Cc: Russell King <linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200409064416.83340-3-sboyd@kernel.org
2020-05-05 12:33:57 -07:00
Stephen Boyd
38d6d84884 ARM: Remove redundant COMMON_CLK selects
The mulitplatform config already selects COMMON_CLK, so selecting it
again is not useful. Remove these selects from ARM platforms that are
part of the multiplatform build.

Reviewed-by: "Andreas Färber" <afaerber@suse.de> # actions
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> # actions
Cc: Russell King <linux@armlinux.org.uk>
Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Lubomir Rintel <lkundrak@v3.sk>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200409064416.83340-2-sboyd@kernel.org
2020-05-05 12:33:50 -07:00
Stephen Boyd
e8b81b1ea3 clk: renesas: Updates for v5.8
- Add support for the USB 2.0 clock selector on R-Car M3-W+,
   - Add support for the new RZ/G1H (R8A7742) SoC,
   - Minor fixes and cleanups.
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Merge tag 'clk-renesas-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add support for the USB 2.0 clock selector on R-Car M3-W+
 - Add support for the new RZ/G1H (R8A7742) SoC
 - Minor fixes and cleanups

* tag 'clk-renesas-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
  clk: renesas: cpg-mssr: Add R8A7742 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
  MAINTAINERS: Add DT Bindings for Renesas Clock Generators
  clk: renesas: r9a06g032: Fix some typo in comments
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
2020-05-05 12:28:46 -07:00
Martin Blumenstingl
a29ae8600d clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers.
In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when
booting Linux the PLL fails to lock.
The initialization sequence from u-boot is:
- put the PLL into reset
- write 0x59C88000 to HHI_GP_PLL_CNTL2
- write 0xCA463823 to HHI_GP_PLL_CNTL3
- write 0x0286A027 to HHI_GP_PLL_CNTL4
- write 0x00003000 to HHI_GP_PLL_CNTL5
- set M, N, OD and the enable bit
- take the PLL out of reset
- check if it has locked
- disable the PLL

In Linux we already initialize M, N, OD, the enable and the reset bits.
Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the
exact meaning is unknown) so the PLL can lock when the vendor u-boot did
not initialize these registers yet.

Fixes: b882964b37 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
2020-05-02 01:53:32 +02:00
Geert Uytterhoeven
e2f022c10e clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
CLK_RENESAS_CPG_MSSR selects CLK_RENESAS_DIV6, and CLK_RCAR_GEN2_CPG
selects CLK_RENESAS_CPG_MSSR, so there is no longer a need for the
individual R-Car Gen2 clock driver options to select CLK_RENESAS_DIV6.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200427193446.29738-1-geert+renesas@glider.be
2020-04-30 09:39:06 +02:00
Lad Prabhakar
e8208a71ac clk: renesas: cpg-mssr: Add R8A7742 support
Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-30 09:38:58 +02:00
Martin Blumenstingl
16afd70af5 clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
The "vpu_0" or "vpu_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1"
tree when "vpu_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the VPU
clock.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-5-martin.blumenstingl@googlemail.com
2020-04-29 10:26:53 +02:00
Martin Blumenstingl
8bb629cfb2 clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL
register:
- HHI_VID_CLK_CNTL[0] = DIV1_EN
- HHI_VID_CLK_CNTL[1] = DIV2_EN
- HHI_VID_CLK_CNTL[2] = DIV4_EN
- HHI_VID_CLK_CNTL[3] = DIV6_EN
- HHI_VID_CLK_CNTL[4] = DIV12_EN

Update the bits accordingly so we will enable the bits in the correct
register once we switch these clocks to be mutable.

Fixes: 6cb57c678b ("clk: meson: meson8b: add the read-only video clock trees")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-4-martin.blumenstingl@googlemail.com
2020-04-29 10:26:53 +02:00
Martin Blumenstingl
0d3051c790 clk: meson: meson8b: Fix the polarity of the RESET_N lines
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means:
- asserting them requires setting the register value to 0
- de-asserting them requires setting the register value to 1

Set the register value accordingly for these two reset lines by setting
the inverted the register value compared to all other reset lines.

Fixes: 189621726b ("clk: meson: meson8b: register the built-in reset controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
2020-04-29 10:26:53 +02:00
Martin Blumenstingl
da1978ac3d clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not
easy to see that the vendor kernel does the same, but it actually does.
meson_clk_pll_ops in mainline still cannot fully recalculate all rates
from the HDMI PLL registers because some register bits (at the time of
writing it's unknown which bits are used for this) double the HDMI PLL
output rate (compared to simply considering M, N and FRAC) for some (but
not all) PLL settings.

Update the vid_pll_in_sel parent so our clock calculation works for
simple clock settings like the CVBS output (where no rate doubling is
going on). The PLL ops need to be fixed later on for more complex clock
settings (all HDMI rates).

Fixes: 6cb57c678b ("clk: meson: meson8b: add the read-only video clock trees")
Suggested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com
2020-04-29 10:26:53 +02:00
Geert Uytterhoeven
07ba856781 Renesas RZ/G1H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G1H (R8A7742) SoC,
 shared by driver and DT source files.
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Merge tag 'renesas-r8a7742-dt-binding-defs-tag' into clk-renesas-for-v5.8

Renesas RZ/G1H DT Binding Definitions

Clock and Power Domain definitions for the Renesas RZ/G1H (R8A7742) SoC,
shared by driver and DT source files.
2020-04-28 10:06:29 +02:00
Lad Prabhakar
6424962816 dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
Add binding documentation for the RZ/G1H (R8A7742) Clock Pulse Generator
driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-28 10:06:24 +02:00
Lad Prabhakar
41b2df22fa clk: renesas: Add r8a7742 CPG Core Clock Definitions
Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
Manual.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-28 09:54:25 +02:00
Lad Prabhakar
58f7381c97 dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
Add power domain indices for RZ/G1H (R8A7742) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-28 09:54:12 +02:00
Geert Uytterhoeven
fdba377f96 MAINTAINERS: Add DT Bindings for Renesas Clock Generators
The "RENESAS CLOCK DRIVERS" section lacks the related DT bindings.
Add them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200417141116.23019-1-geert+renesas@glider.be
2020-04-20 10:40:38 +02:00
Martin Blumenstingl
6dde0ae30a clk: meson: g12a: Prepare the GPU clock tree to change at runtime
The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.
Also propagate set_rate requests from the gate to the divider and from
the divider to the the mux so the GPU clock frequency can be updated at
runtime (which will be required for GPU DVFS). Don't propagate rate
changes to the mux parents because we don't want to change the MPLL
clocks (these are reserved for audio).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200414195031.224021-3-martin.blumenstingl@googlemail.com
2020-04-16 12:23:05 +02:00
Martin Blumenstingl
5c2602e5fc clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.
Also propagate set_rate requests from the gate to the divider and from
the divider to the the mux so the GPU clock frequency can be updated at
runtime (which will be required for GPU DVFS). Don't propagate rate
changes to the mux parents because we don't want to change the MPLL
clocks (these are reserved for audio).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200414195031.224021-2-martin.blumenstingl@googlemail.com
2020-04-16 12:23:05 +02:00
Martin Blumenstingl
f0e0884acf clk: meson: meson8b: make the hdmi_sys clock tree mutable
The HDMI TX controller requires the hdmi_sys clock to be enabled. Allow
changing the whole clock tree now that we know that one of our drivers
requires this.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200330234535.3327513-3-martin.blumenstingl@googlemail.com
2020-04-14 14:29:23 +02:00
Martin Blumenstingl
778fb6b729 clk: meson8b: export the HDMI system clock
Export the HDMI system clock (used by the HDMI transmitter) so it can be
used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200330234535.3327513-2-martin.blumenstingl@googlemail.com
2020-04-14 14:28:34 +02:00
Christophe JAILLET
cdfdeb4a38 clk: renesas: r9a06g032: Fix some typo in comments
This file seems to be for R9A06G032 only. So replace reference to
R9A09G032 by R9A06G032 to avoid confusion.

AFAIK, R9A09G032 does'nt exist.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/20200413041709.3630-1-christophe.jaillet@wanadoo.fr
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-14 09:22:16 +02:00
Yoshihiro Shimoda
91a577e77f dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
This patch adds support for r8a77961 (R-Car M3-W+).

To avoid confusion between R-Car M3-W (R8A77960) and R-Car M3-W+
(R8A77961), this patch also updates the comment of
"renesas,r8a7796-rcar-usb2-clock-sel".

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1585200608-30103-1-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-14 09:21:58 +02:00
Rikard Falkeborn
ee25d9742d
clk: sunxi: Fix incorrect usage of round_down()
round_down() can only round to powers of 2. If round_down() is asked
to round to something that is not a power of 2, incorrect results are
produced. The incorrect results can be both too large and too small.

Instead, use rounddown() which can round to any number.

Fixes: 6a721db180 ("clk: sunxi: Add A31 clocks support")
Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2020-04-14 09:21:05 +02:00
Linus Torvalds
8f3d9f3542 Linux 5.7-rc1 v5.7-rc1 2020-04-12 12:35:55 -07:00
Linus Torvalds
3b50142d85 MAINTAINERS: sort field names for all entries
This sorts the actual field names too, potentially causing even more
chaos and confusion at merge time if you have edited the MAINTAINERS
file.  But the end result is a more consistent layout, and hopefully
it's a one-time pain minimized by doing this just before the -rc1
release.

This was entirely scripted:

  ./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS --order

Requested-by: Joe Perches <joe@perches.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-04-12 11:04:58 -07:00
Linus Torvalds
4400b7d68f MAINTAINERS: sort entries by entry name
They are all supposed to be sorted, but people who add new entries don't
always know the alphabet.  Plus sometimes the entry names get edited,
and people don't then re-order the entry.

Let's see how painful this will be for merging purposes (the MAINTAINERS
file is often edited in various different trees), but Joe claims there's
relatively few patches in -next that touch this, and doing it just
before -rc1 is likely the best time.  Fingers crossed.

This was scripted with

  /scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS

but then I also ended up manually upper-casing a few entry names that
stood out when looking at the end result.

Requested-by: Joe Perches <joe@perches.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-04-12 11:03:52 -07:00
Linus Torvalds
4f8a3cc118 A set of three patches to fix the fallout of the newly added split lock
detection feature.
 
 It addressed the case where a KVM guest triggers a split lock #AC and KVM
 reinjects it into the guest which is not prepared to handle it.
 
 Adds proper sanity checks which prevent the unconditional injection into
 the guest and handles the #AC on the host side in the same way as user
 space detections are handled. Depending on the detection mode it either
 warns and disables detection for the task or kills the task if the mode is
 set to fatal.
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Merge tag 'x86-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Thomas Gleixner:
 "A set of three patches to fix the fallout of the newly added split
  lock detection feature.

  It addressed the case where a KVM guest triggers a split lock #AC and
  KVM reinjects it into the guest which is not prepared to handle it.

  Add proper sanity checks which prevent the unconditional injection
  into the guest and handles the #AC on the host side in the same way as
  user space detections are handled. Depending on the detection mode it
  either warns and disables detection for the task or kills the task if
  the mode is set to fatal"

* tag 'x86-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  KVM: VMX: Extend VMXs #AC interceptor to handle split lock #AC in guest
  KVM: x86: Emulate split-lock access as a write in emulator
  x86/split_lock: Provide handle_guest_split_lock()
2020-04-12 10:17:16 -07:00
Linus Torvalds
0785249f8b Time(keeping) updates:
- Fix the time_for_children symlink in /proc/$PID/ so it properly reflects
    that it part of the 'time' namespace
 
  - Add the missing userns limit for the allowed number of time namespaces,
    which was half defined but the actual array member was not added.  This
    went unnoticed as the array has an exessive empty member at the end but
    introduced a user visible regression as the output was corrupted.
 
  - Prevent further silent ucount corruption by adding a BUILD_BUG_ON() to
    catch half updated data.
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Merge tag 'timers-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull time(keeping) updates from Thomas Gleixner:

 - Fix the time_for_children symlink in /proc/$PID/ so it properly
   reflects that it part of the 'time' namespace

 - Add the missing userns limit for the allowed number of time
   namespaces, which was half defined but the actual array member was
   not added. This went unnoticed as the array has an exessive empty
   member at the end but introduced a user visible regression as the
   output was corrupted.

 - Prevent further silent ucount corruption by adding a BUILD_BUG_ON()
   to catch half updated data.

* tag 'timers-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  ucount: Make sure ucounts in /proc/sys/user don't regress again
  time/namespace: Add max_time_namespaces ucount
  time/namespace: Fix time_for_children symlink
2020-04-12 10:13:14 -07:00
Linus Torvalds
590680d139 Scheduler fixes/updates:
- Deduplicate the average computations in the scheduler core and the fair
    class code.
 
  - Fix a raise between runtime distribution and assignement which can cause
    exceeding the quota by up to 70%.
 
  - Prevent negative results in the imbalanace calculation
 
  - Remove a stale warning in the workqueue code which can be triggered
    since the call site was moved out of preempt disabled code. It's a false
    positive.
 
  - Deduplicate the print macros for procfs
 
  - Add the ucmap values to the SCHED_DEBUG procfs output for completness
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Merge tag 'sched-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull scheduler fixes/updates from Thomas Gleixner:

 - Deduplicate the average computations in the scheduler core and the
   fair class code.

 - Fix a raise between runtime distribution and assignement which can
   cause exceeding the quota by up to 70%.

 - Prevent negative results in the imbalanace calculation

 - Remove a stale warning in the workqueue code which can be triggered
   since the call site was moved out of preempt disabled code. It's a
   false positive.

 - Deduplicate the print macros for procfs

 - Add the ucmap values to the SCHED_DEBUG procfs output for completness

* tag 'sched-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  sched/debug: Add task uclamp values to SCHED_DEBUG procfs
  sched/debug: Factor out printing formats into common macros
  sched/debug: Remove redundant macro define
  sched/core: Remove unused rq::last_load_update_tick
  workqueue: Remove the warning in wq_worker_sleeping()
  sched/fair: Fix negative imbalance in imbalance calculation
  sched/fair: Fix race between runtime distribution and assignment
  sched/fair: Align rq->avg_idle and rq->avg_scan_cost
2020-04-12 10:09:19 -07:00
Linus Torvalds
20e2aa8126 Thre fixes/updates for perf:
- Fix the perf event cgroup tracking which tries to track the cgroup even
    for disabled events.
 
  - Add Ice Lake server support for uncore events
 
  - Disable pagefaults when retrieving the physical address in the sampling
    code.
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Merge tag 'perf-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Thomas Gleixner:
 "Three fixes/updates for perf:

   - Fix the perf event cgroup tracking which tries to track the cgroup
     even for disabled events.

   - Add Ice Lake server support for uncore events

   - Disable pagefaults when retrieving the physical address in the
     sampling code"

* tag 'perf-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/core: Disable page faults when getting phys address
  perf/x86/intel/uncore: Add Ice Lake server uncore support
  perf/cgroup: Correct indirection in perf_less_group_idx()
  perf/core: Fix event cgroup tracking
2020-04-12 10:05:24 -07:00
Linus Torvalds
652fa53caa Three small fixes/updates for the locking core code:
- Plug a task struct reference leak in the percpu rswem implementation.
 
  - Document the refcount interaction with PID_MAX_LIMIT
 
  - Improve the 'invalid wait context' data dump in lockdep so it contains
    all information which is required to decode the problem
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Merge tag 'locking-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull locking fixes from Thomas Gleixner:
 "Three small fixes/updates for the locking core code:

   - Plug a task struct reference leak in the percpu rswem
     implementation.

   - Document the refcount interaction with PID_MAX_LIMIT

   - Improve the 'invalid wait context' data dump in lockdep so it
     contains all information which is required to decode the problem"

* tag 'locking-urgent-2020-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  locking/lockdep: Improve 'invalid wait context' splat
  locking/refcount: Document interaction with PID_MAX_LIMIT
  locking/percpu-rwsem: Fix a task_struct refcount
2020-04-12 09:47:10 -07:00