With support of interrupt based mechanism, gpio is not longer set to
output mode, so gpio_set_value won't work. So use
gpio_direction_output() fn in poweroff(), while setting value on
wake/detect line.
Testing Done: Tested on DB3.5 platform.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Reviewed-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Since now driver supports interrupt based mechanism to read events
from SVC over wake/detect line, no need to delay wake/detect assertion.
We can assert wake/detect after SVC reset deassertion, so during boot
itself SVC will start sending wake_out pulses.
Testing Done: Tested on DB3.5 platform.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Reviewed-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This patch enabled interrupt support on events received over wake/detect
line. The driver follows below state machine,
Default: wake/detect line is high (WD_STATE_IDLE)
On Falling edge:
SVC initiates boot (either cold/standby).
On ES3, > 30msec = coldboot, else standby boot.
Driver moves to WD_STATE_BOOT_INIT
On rising edge (> 30msec):
SVC expects APB to coldboot
Driver wakes irq thread which kicks off APB coldboot
(WD_STATE_COLDBOOT_TRIG)
On rising edge (< 30msec):
Driver ignores it, do nothing.
After coldboot of APB, HUB configuration work is scheduled after 2 sec,
allowing enough time for APB<->SVC/Switch to linkup (in multiple
iterations)
Testing Done: Tested on DB3.5 platform.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Reviewed-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
If driver needs to process wake/detect events from SVC, by enabling
interrupt support on wake/detect event, it becomes easier to maintain
state of wake/detect line based on functionality.
Testing Done: Tested on DB3.5 platform.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Reviewed-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This is preparation of interrupt handling support, where APB coldboot
and wake/detect handling will be handled as response to wake/detect
interrupt.
Due to slower I2C write operations in HUB configuration, it is important
to separate HUB configuration, and probably delay it after APB is
cold booted.
Note that delayed work will be scheduled from interrupt handler,
in following patches.
To satisfy build (and bisect), remove apb_cold_boot() fn, which will be
added back in the patch where it gets used again.
Testing Done: Tested on DB3.5 platform.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Reviewed-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
With synchronization between SVC <=> AP over wake/detect line to
bring APB's out of reset, we do not need any extra delays now.
So remove it.
Testing Done: Tested for DB3.5 and EVT1.2 platform.
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Reviewed-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Make example module 1-5 a 2x2 module by adding a second, dummy
interface.
This is both an example of how a 2x2 module would be represented and
also suggests what a dummy interface may look like.
A 2x2 module has two child interface devices and a num_interfaces value
of two.
In this example, the secondary interface 1-5.6, is a dummy interface and
therefore lacks the normal identifying attributes (e.g. UniPro DDBL1 and
Ara ids). We may eventually add an interface_type attribute to
facilitate distinguishing various interface types (there may be more
than two).
In the following tree, the bundle attributes and child devices have been
left out:
greybus1/
├── 1-2
│ ├── 1-2.2
│ │ ├── 1-2.2.1
│ │ ├── 1-2.2.2
│ │ ├── ddbl1_manufacturer_id
│ │ ├── ddbl1_product_id
│ │ ├── interface_id
│ │ ├── product_id
│ │ ├── serial_number
│ │ ├── unique_id
│ │ └── vendor_id
│ ├── eject
│ ├── module_id
│ └── num_interfaces
├── 1-5
│ ├── 1-5.5
│ │ ├── 1-5.5.2
│ │ ├── ddbl1_manufacturer_id
│ │ ├── ddbl1_product_id
│ │ ├── interface_id
│ │ ├── product_id
│ │ ├── serial_number
│ │ ├── unique_id
│ │ └── vendor_id
│ ├── 1-5.6
│ │ └── interface_id
│ ├── eject
│ ├── module_id
│ └── num_interfaces
└── 1-svc
In this example there are two modules: 1-2 is a 1x2 module with one
interface, and 1-5 is a 2x2 module with two interfaces of which the
second (1-5.6) is a dummy interface.
Signed-off-by: Johan Hovold <johan@hovoldconsulting.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Move example module 1-4 to position 5, effectively renaming it 1-5.
Signed-off-by: Johan Hovold <johan@hovoldconsulting.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Introduce module devices and rename interface and bundle devices.
Greybus module devices correspond to physical modules and have one or
more interfaces. Modules have an id that is identical to the id of their
primary interface, which in turn is the interface with lowest numbered
id. The module name is constructed from the bus and module id:
<bus_id>-<module_id>
Interfaces and bundles are consequently renamed as
<bus_id>-<module_id>.<interface_id>
and
<bus_id>-<module_id>.<interface_id>.<bundle_id>
respectively.
As before, interface ids (and therefore in a sense now also module ids)
correspond to physical interface positions on the frame.
Modules have the following attributes:
eject
module_id
num_interfaces
where module_id is the id of the module and num_interface the number of
interfaces the module has.
Note that the interface ids of a module's interfaces are expected to be
<module_id>, <module_id + 1>, ..., <module_id + num_interfaces - 1>.
Writing a non-zero argument to eject cleanly shuts down and unregisters
all of the module interfaces before ejecting the module.
The example sysfs tree now looks as follows with the second bus
(APBridgeA) left out:
greybus1/
├── 1-2
│ ├── 1-2.2
│ │ ├── 1-2.2.1
│ │ │ ├── bundle_class
│ │ │ ├── bundle_id
│ │ │ └── state
│ │ ├── 1-2.2.2
│ │ │ ├── bundle_class
│ │ │ ├── bundle_id
│ │ │ └── state
│ │ ├── ddbl1_manufacturer_id
│ │ ├── ddbl1_product_id
│ │ ├── interface_id
│ │ ├── product_id
│ │ ├── serial_number
│ │ ├── unique_id
│ │ └── vendor_id
│ ├── eject
│ ├── module_id
│ └── num_interfaces
├── 1-4
│ ├── 1-4.4
│ │ ├── 1-4.4.2
│ │ │ ├── bundle_class
│ │ │ ├── bundle_id
│ │ │ ├── gpbridge0
│ │ │ │ ├── gpio
│ │ │ │ │ └── gpiochip490
│ │ │ │ └── i2c-4
│ │ │ └── state
│ │ ├── ddbl1_manufacturer_id
│ │ ├── ddbl1_product_id
│ │ ├── interface_id
│ │ ├── product_id
│ │ ├── serial_number
│ │ ├── unique_id
│ │ └── vendor_id
│ ├── eject
│ ├── module_id
│ └── num_interfaces
└── 1-svc
├── ap_intf_id
├── eject
└── endo_id
where greybus1 is a bus; 1-svc the svc; 1-2, and 1-4 are modules; 1-2.2
and 1-4.4 are (primary) interfaces; and 1-2.2.1, 1-2.2.2, and 1-4.4.2
are bundles.
Note that the svc eject attribute may eventually be renamed force_eject.
Signed-off-by: Johan Hovold <johan@hovoldconsulting.com>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
Vybrid) whereas the register enumeration start from 1 (1-10 for
LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
iterations and initialized the number of layers inclusive, which
is one layer too many.
All extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The current default configuration is as follows:
- Invert VSYNC signal (active LOW)
- Invert HSYNC signal (active LOW)
The mode flags allow to specify the required polarity per
mode. Furthermore, none of the current driver settings is
actually a standard polarity.
This patch applies the current driver default polarities as
explicit flags to the display which has been introduced with
the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now
also parses the flags field and applies the configuration
accordingly, by using the following values as standard
polarities: (e.g. when no flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Fix alpha blending by enabling alpha blending for the whole frame if
a color mode with alpha channel is selected (DRM_FORMAT_ARGB*). Also
support color modes without alpha channel (DRM_FORMAT_XRGB*) by just
not enabling alpha blending on layer level.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The state of the interrupt mask register on initialization is
unknown, e.g. U-Boot could already used the DCU. So depending on
the boot loader, the outcome of the interrupt mask register could
be different. A defined state is much more preferable. Also, there
is no value in keeping interrupts enabled which we don't need.
Therefor, mask all interrupts on initialization.
Signed-off-by: Stefan Agner <stefan@agner.ch>
If initialization fails (e.g. due to missing panel node or deferred
probe) make sure to roll-back all operations and return the error
code.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Improve error handling during CRTC initialization. Especially avoid
memory leaks in the primary plane initialization error path.
Signed-off-by: Stefan Agner <stefan@agner.ch>
It is not common to do regmap return value checks, especially not
for memory mapped device. We can rule out most error returns since
the conditions are static and we know they are ok (e.g. offset
aligned to register stride). Also without proper error handling
they are not really valuable for the user. Hence remove most of
them.
The check in the interrupt handler is worth keeping since a
volatile register won't be readable in case register caching is
still enabled.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.
Signed-off-by: Stefan Agner <stefan@agner.ch>
For state->fb or state->crtc may be NULL in fsl_dcu_drm_plane_atomic_check
function, if so, return 0.
Signed-off-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Promote myself as new maintainer of the Freescale DCU DRM driver.
Acked-by: Jianwei Wang <jianwei.wang.chn@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
We should set SW15 to pin 2-3 side on the board before we use CN9
as USB host or peripheral.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This board has a MAX3355 chip. However, we cannot use the extcon/max3355
driver because the ID pin doesn't connect to a gpio pin (in other words,
it connects to the SoC specific pin).
And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now.
So, this patch enables usb2_phy of channel 1 and 2.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support.
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: squashed some fixes and added mmc-caps]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
s3c24xx implements its own inb/outb macros, but the implementation
prints warnings when the port number argument is not a 32-bit scalar:
drivers/scsi/pas16.c: In function 'NCR5380_pwrite':
arch/arm/mach-s3c24xx/include/mach/io.h:193:68: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
This slightly modifies the definition of the __ioaddrc macro to avoid
the warning.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
As of 9b5ba0df4e ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.
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Merge tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk driver changes from Sylwester Nawrocki:
Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.
* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
clk: samsung: exynos5433: Drop RO registers from the save/restore lists
clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
clk/samsung: exynos5433: add pclk_decon clock
clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
The core clock does not depend on corediv, so enabling corediv
based on the clock is not really correct. Move the corediv
config option from the clock driver Kconfig to the mvebu Kconfig
so that it can be enabled by the MACH option instead.
This also enables corediv on Armada 375 and 38X, which was
previously missing.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There is no corediv clock on Armada XP, so this is unnecessary.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.
Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.
This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
(show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
(dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
(warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
(warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
(clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
(of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
(time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
(start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c43 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch updates the digital voltage levels from corner values to
microvolts as we are going to use s1 regulator directly for vddcx
instead of s1_corner.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch enables the lpass on DB410C. LPASS is used as cpu dai for
both analog and digital audio.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
This patch adds manual pull up setting for usb otg indicating that the
vbus is vbus is not routed to USB controller/phy therefore enables
pull-up explicitly before starting controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
By default, not only this driver is enabled on all platforms, but also
generic PM Domains and Multi-Function Devices.
Drop the "default y" to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When I reworked this code, I messed up num rb count.
v2: use hweight32
Reviewed-by: Ken Wang <Qingquing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Joshua Henderson <joshua.henderson@microchip.com>
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
msg.dst_sk needs to be set up with a valid socket because some callbacks
later derive the netns from it.
Fixes: 263ea09084d172d ("Revert "genl: Add genlmsg_new_unicast() for unicast message allocation")
Reported-by: Jon Maloy <maloy@donjonn.com>
Bisected-by: Jon Maloy <maloy@donjonn.com>
Signed-off-by: Florian Westphal <fw@strlen.de>
Acked-by Jon Maloy <jon.maloy@ericsson.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
When the TIPC module is unloaded, we have identified a race condition
that allows a node reference counter to go to zero and the node instance
being freed before the node timer is finished with accessing it. This
leads to occasional crashes, especially in multi-namespace environments.
The scenario goes as follows:
CPU0:(node_stop) CPU1:(node_timeout) // ref == 2
1: if(!mod_timer())
2: if (del_timer())
3: tipc_node_put() // ref -> 1
4: tipc_node_put() // ref -> 0
5: kfree_rcu(node);
6: tipc_node_get(node)
7: // BOOM!
We now clean up this functionality as follows:
1) We remove the node pointer from the node lookup table before we
attempt deactivating the timer. This way, we reduce the risk that
tipc_node_find() may obtain a valid pointer to an instance marked
for deletion; a harmless but undesirable situation.
2) We use del_timer_sync() instead of del_timer() to safely deactivate
the node timer without any risk that it might be reactivated by the
timeout handler. There is no risk of deadlock here, since the two
functions never touch the same spinlocks.
3: We remove a pointless tipc_node_get() + tipc_node_put() from the
timeout handler.
Reported-by: Zhijiang Hu <huzhijiang@gmail.com>
Acked-by: Ying Xue <ying.xue@windriver.com>
Signed-off-by: Jon Maloy <jon.maloy@ericsson.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
