Running AIO is pinning inode in memory using file reference. Once AIO
is completed using aio_complete(), file reference is put and inode can
be freed from memory. So we have to be sure that calling aio_complete()
is the last thing we do with the inode.
CC: xfs@oss.sgi.com
CC: Ben Myers <bpm@sgi.com>
CC: stable@vger.kernel.org
Signed-off-by: Jan Kara <jack@suse.cz>
Reviewed-by: Ben Myers <bpm@sgi.com>
Signed-off-by: Ben Myers <bpm@sgi.com>
When the new inode verify in xfs_iread() fails, the create
transaction is aborted and a shutdown occurs. The subsequent unmount
then hangs in xfs_wait_buftarg() on a buffer that has an elevated
hold count. Debug showed that it was an AGI buffer getting stuck:
[ 22.576147] XFS (vdb): buffer 0x2/0x1, hold 0x2 stuck
[ 22.976213] XFS (vdb): buffer 0x2/0x1, hold 0x2 stuck
[ 23.376206] XFS (vdb): buffer 0x2/0x1, hold 0x2 stuck
[ 23.776325] XFS (vdb): buffer 0x2/0x1, hold 0x2 stuck
The trace of this buffer leading up to the shutdown (trimmed for
brevity) looks like:
xfs_buf_init: bno 0x2 nblks 0x1 hold 1 caller xfs_buf_get_map
xfs_buf_get: bno 0x2 len 0x200 hold 1 caller xfs_buf_read_map
xfs_buf_read: bno 0x2 len 0x200 hold 1 caller xfs_trans_read_buf_map
xfs_buf_iorequest: bno 0x2 nblks 0x1 hold 1 caller _xfs_buf_read
xfs_buf_hold: bno 0x2 nblks 0x1 hold 1 caller xfs_buf_iorequest
xfs_buf_rele: bno 0x2 nblks 0x1 hold 2 caller xfs_buf_iorequest
xfs_buf_iowait: bno 0x2 nblks 0x1 hold 1 caller _xfs_buf_read
xfs_buf_ioerror: bno 0x2 len 0x200 hold 1 caller xfs_buf_bio_end_io
xfs_buf_iodone: bno 0x2 nblks 0x1 hold 1 caller _xfs_buf_ioend
xfs_buf_iowait_done: bno 0x2 nblks 0x1 hold 1 caller _xfs_buf_read
xfs_buf_hold: bno 0x2 nblks 0x1 hold 1 caller xfs_buf_item_init
xfs_trans_read_buf: bno 0x2 len 0x200 hold 2 recur 0 refcount 1
xfs_trans_brelse: bno 0x2 len 0x200 hold 2 recur 0 refcount 1
xfs_buf_item_relse: bno 0x2 nblks 0x1 hold 2 caller xfs_trans_brelse
xfs_buf_rele: bno 0x2 nblks 0x1 hold 2 caller xfs_buf_item_relse
xfs_buf_unlock: bno 0x2 nblks 0x1 hold 1 caller xfs_trans_brelse
xfs_buf_rele: bno 0x2 nblks 0x1 hold 1 caller xfs_trans_brelse
xfs_buf_trylock: bno 0x2 nblks 0x1 hold 2 caller _xfs_buf_find
xfs_buf_find: bno 0x2 len 0x200 hold 2 caller xfs_buf_get_map
xfs_buf_get: bno 0x2 len 0x200 hold 2 caller xfs_buf_read_map
xfs_buf_read: bno 0x2 len 0x200 hold 2 caller xfs_trans_read_buf_map
xfs_buf_hold: bno 0x2 nblks 0x1 hold 2 caller xfs_buf_item_init
xfs_trans_read_buf: bno 0x2 len 0x200 hold 3 recur 0 refcount 1
xfs_trans_log_buf: bno 0x2 len 0x200 hold 3 recur 0 refcount 1
xfs_buf_item_unlock: bno 0x2 len 0x200 hold 3 flags DIRTY liflags ABORTED
xfs_buf_unlock: bno 0x2 nblks 0x1 hold 3 caller xfs_buf_item_unlock
xfs_buf_rele: bno 0x2 nblks 0x1 hold 3 caller xfs_buf_item_unlock
And that is the AGI buffer from cold cache read into memory to
transaction abort. You can see at transaction abort the bli is dirty
and only has a single reference. The item is not pinned, and it's
not in the AIL. Hence the only reference to it is this transaction.
The problem is that the xfs_buf_item_unlock() call is dropping the
last reference to the xfs_buf_log_item attached to the buffer (which
holds a reference to the buffer), but it is not freeing the
xfs_buf_log_item. Hence nothing will ever release the buffer, and
the unmount hangs waiting for this reference to go away.
The fix is simple - xfs_buf_item_unlock needs to detect the last
reference going away in this case and free the xfs_buf_log_item to
release the reference it holds on the buffer.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Ben Myers <bpm@sgi.com>
Signed-off-by: Ben Myers <bpm@sgi.com>
There is a window on small filesytsems where specualtive
preallocation can be larger than that ENOSPC throttling thresholds,
resulting in specualtive preallocation trying to reserve more space
than there is space available. This causes immediate ENOSPC to be
triggered, prealloc to be turned off and flushing to occur. One the
next write (i.e. next 4k page), we do exactly the same thing, and so
effective drive into synchronous 4k writes by triggering ENOSPC
flushing on every page while in the window between the prealloc size
and the ENOSPC prealloc throttle threshold.
Fix this by checking to see if the prealloc size would consume all
free space, and throttle it appropriately to avoid premature
ENOSPC...
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Signed-off-by: Ben Myers <bpm@sgi.com>
When _xfs_buf_find is passed an out of range address, it will fail
to find a relevant struct xfs_perag and oops with a null
dereference. This can happen when trying to walk a filesystem with a
metadata inode that has a partially corrupted extent map (i.e. the
block number returned is corrupt, but is otherwise intact) and we
try to read from the corrupted block address.
In this case, just fail the lookup. If it is readahead being issued,
it will simply not be done, but if it is real read that fails we
will get an error being reported. Ideally this case should result
in an EFSCORRUPTED error being reported, but we cannot return an
error through xfs_buf_read() or xfs_buf_get() so this lookup failure
may result in ENOMEM or EIO errors being reported instead.
Signed-off-by: Dave Chinner <dchinner@redhat.com>
Reviewed-by: Brian Foster <bfoster@redhat.com>
Reviewed-by: Ben Myers <bpm@sgi.com>
Signed-off-by: Ben Myers <bpm@sgi.com>
The stack_switch check currently occurs in __xfs_bmapi_allocate,
which means the stack switch only occurs when xfs_bmapi_allocate()
is called in a loop. Pull the check up before the loop in
xfs_bmapi_write() such that the first iteration of the loop has
consistent behavior.
Signed-off-by: Brian Foster <bfoster@redhat.com>
Reviewed-by: Dave Chinner <dchinner@redhat.com>
Signed-off-by: Ben Myers <bpm@sgi.com>
9802182 changed the return value from EWRONGFS (aka EINVAL)
to EFSCORRUPTED which doesn't seem to be handled properly by
the root filesystem probe.
Signed-off-by: Eric Sandeen <sandeen@redhat.com>
Tested-by: Sergei Trofimovich <slyfox@gentoo.org>
Reviewed-by: Ben Myers <bpm@sgi.com>
Signed-off-by: Ben Myers <bpm@sgi.com>
As pointer to PHY structure can be stored in struct usb_hcd
making use of it, to call Tegra PHY APIs.
Call to usb_phy_shutdown() is moved up in tegra_ehci_remove(),
so that to avoid dereferencing of hcd after its freed up.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
As reset GPIO information is PHY specific detail, adding
it to PHY DT node.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the device tree for the Toradex Iris carrier board used
together with a Colibri T20 512MB COM.
The Iris has the following features, in brackets the current status:
- DVI and VGA output through DVI-I connector (DVI-D enabled and tested)
- LVDS output
- 1 USB host port (enabled and tested)
- 1 USB OTG port (enabled)
- 100 MBit Ethernet (enabled and tested)
- 5 UART ports (2 on 10way headers enabled and tested)
- 1 MicroSD Slot (enabled and tested)
- Audio connectors (enabled, only HP out and Line-in tested)
- i2c RTC
- GPIO connector (enabled, only sparsely tested)
- external i2c bus
- 4 PWM out
- analog in
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the device tree include file for the Toradex Colibri T20
Computer on Module (COM). It's only valid for the 512MB RAM version of
the module, as the 256MB version needs different EMC tables and flash
configuration. To make this clear the suffix -512 was added to the board
compatible string.
The Colibri T20 uses a Tegra20 SoC and has onboard USB Ethernet and AC97
sound.
Still some things like onboard NAND support missing, but should be a
good base for further development.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable Tegra based keyboard interfacing for keys and provide
all key mapping through DTS file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable Tegra based keyboard controller and populate the key mapping
for Whistler.
With this patch, HOME, BACK, POWER and MENU keys will work.
Still other keys which are in ROW3 and ROW4 will not work as it
conflicts with KBC pins on SDIO2 pinmux.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
UARTC is used for the interfacing with bluetooth device.
Register this UART channel as high speed serial channel
so that it can use the APB DMA for data transfer.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable Tegra based keyboard controller and populate the key matrix for
seaboard. The key matrix was originally on driver code which is removed
to have clean driver. The key mapping is now passed through dts file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra SoCs have the matrix keyboard controller which
supports 16x8 type of matrix. The number of rows and columns
are configurable.
Add DT entry for KBC controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: added clocks property]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This ensures nodes are sorted in order of reg address. This makes it
easier to compare against e.g. the U-Boot device trees, and is simply
consistent and clean.
While we're at it, remove the unit address from the cache-controller
node name, since it's unique without it.
Reported-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds support for Tegra30 Beaver board in upstream kernel.
Beaver board is a Tegra30 SoC based development board, it has
following features:
- T30 or T33 SoC (Qual core ARM Cortex A9)
- 2 GB DDR3L
- 16 GB EMMC
- 1 SD slot
- 1 USB Standart A port and 1 USB micro AB port
- PCI-E Gig Ethernet
- Audio input/output
- SATA port
- HDMI output
- UART and JTAG
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The compatible properties of Tegra SoC based boards or machines need
to be documented. This patch adds these board levle compatible
properties into device tree binding document.
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add APB DMA requestor and serial aliases for serial controller.
There will be two serial driver i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.
The simple serial driver get enabled with compatible nvidia,tegra20-uart
and APB DMA based driver will get enabled with compatible
nvidia,tegra20-hsuart.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
tegra30 gpio controller is not compatible with the tegra20 due to
their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30
bank stride is 0x100.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed typo syntax error]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a new evaluation board, Pluto for Tegra 114 family.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a new evaluation board, Dalmore for Tegra 114 family.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Initial support for Tegra 114 SoC. This is expected to be included in
the board DTS files, Tegra 114 SoC based evaluation board family.
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20 had a limition to
power down both CPU cores. The secondary CPU must waits for CPU0 in
powered-down state too. If the secondary CPU be woken up before CPU0
entering powered-down state, then it needs to restore its CPU states
and waits for next chance.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
include the power of GIC. That caused the SGI (Software Generated
Interrupt) been lost. Because the SGI can't wake up the CPU that in
the "powered-down" CPU idle mode. We need to check if there is any
pending SGI when go into "powered-down" CPU idle mode. This is important
especially when applying the coupled cpuidle framework into "power-down"
cpuidle dirver. Because the coupled cpuidle framework may have the
chance that misses IPI_SINGLE_FUNC handling sometimes.
For the PPI or SPI, something like the legacy peripheral interrupt. It
still can be maintained by Tegra legacy interrupt controller. If there
is any pending PPI or SPI when CPU in "powered-down" CPU idle mode. The
CPU can be woken up immediately. So we don't need to take care the same
situation for PPI or SPI.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Clock "emc" is for the External Memory Controller. The USB driver has no
business touching this clock directly. Remove the code that does so.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
As Tegra PHY driver needs to access one of the host registers,
added few APIs.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
[swarren: moved assignment of phy->is_ulpi_phy to previous patch.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra20 USB has 3 PHY instances:
Instance 1 and 3 are UTMI. Instance 2 is ULPI.
As instance number was used to differentiate ULPI from UTMI,
used DT param to get this info and processed accordingly.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Felipe Balbi <balbi@ti.com>
[swarren: moved assignment of phy->is_ulpi_phy into this patch out
of next patch.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra20 USB has 3 PHY instances. Instance 0 is based on
legacy PHY interface and other two are standard interfaces.
As instance number was used to differentiate legacy from
standard interfaces, used DT param to get this info and
processed accordingly.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The patch to add USB PHY nodes to device tree was written before Tegra
supported the clocks property in device tree. Now that it does, add the
required clocks properties to these nodes.
This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced
by clk_get(phy->dev, clock_name), as part of converting the PHY driver to
a platform driver.
Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add DT nodes for Tegra USB PHY along with related documentation.
Also added a phandle property to controller DT node, for referring
to connected PHY instance.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
As tegra_usb_phy_clk_disable/enable() are not being
used, removing them.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra USB host driver is using port instance number,
to handle some of the hardware issues on SOC e.g. reset PORT0
twice etc. As instance number based handling looks ugly,
making use of information passed through DT for achieving this.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
As Tegra USB host driver is using instance number for resetting
PORT0 twice, adding a new DT property for handling this.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
