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Author SHA1 Message Date
Marcel Ziswiler
df0935f04d ARM: dts: vf-colibri: fix typo in top-level module compatible
Fix typo in top-level module compatible.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-04 09:27:12 +08:00
Francesco Ruggeri
fac6fce9bd net: icmp6: provide input address for traceroute6
traceroute6 output can be confusing, in that it shows the address
that a router would use to reach the sender, rather than the address
the packet used to reach the router.
Consider this case:

        ------------------------ N2
         |                    |
       ------              ------  N3  ----
       | R1 |              | R2 |------|H2|
       ------              ------      ----
         |                    |
        ------------------------ N1
                  |
                 ----
                 |H1|
                 ----

where H1's default route is through R1, and R1's default route is
through R2 over N2.
traceroute6 from H1 to H2 shows R2's address on N1 rather than on N2.

The script below can be used to reproduce this scenario.

traceroute6 output without this patch:

traceroute to 2000:103::4 (2000:103::4), 30 hops max, 80 byte packets
 1  2000:101::1 (2000:101::1)  0.036 ms  0.008 ms  0.006 ms
 2  2000:101::2 (2000:101::2)  0.011 ms  0.008 ms  0.007 ms
 3  2000:103::4 (2000:103::4)  0.013 ms  0.010 ms  0.009 ms

traceroute6 output with this patch:

traceroute to 2000:103::4 (2000:103::4), 30 hops max, 80 byte packets
 1  2000:101::1 (2000:101::1)  0.056 ms  0.019 ms  0.006 ms
 2  2000:102::2 (2000:102::2)  0.013 ms  0.008 ms  0.008 ms
 3  2000:103::4 (2000:103::4)  0.013 ms  0.009 ms  0.009 ms

#!/bin/bash
#
#        ------------------------ N2
#         |                    |
#       ------              ------  N3  ----
#       | R1 |              | R2 |------|H2|
#       ------              ------      ----
#         |                    |
#        ------------------------ N1
#                  |
#                 ----
#                 |H1|
#                 ----
#
# N1: 2000:101::/64
# N2: 2000:102::/64
# N3: 2000:103::/64
#
# R1's host part of address: 1
# R2's host part of address: 2
# H1's host part of address: 3
# H2's host part of address: 4
#
# For example:
# the IPv6 address of R1's interface on N2 is 2000:102::1/64
#
# Nets are implemented by macvlan interfaces (bridge mode) over
# dummy interfaces.
#

# Create net namespaces
ip netns add host1
ip netns add host2
ip netns add rtr1
ip netns add rtr2

# Create nets
ip link add net1 type dummy; ip link set net1 up
ip link add net2 type dummy; ip link set net2 up
ip link add net3 type dummy; ip link set net3 up

# Add interfaces to net1, move them to their nemaspaces
ip link add link net1 dev host1net1 type macvlan mode bridge
ip link set host1net1 netns host1
ip link add link net1 dev rtr1net1 type macvlan mode bridge
ip link set rtr1net1 netns rtr1
ip link add link net1 dev rtr2net1 type macvlan mode bridge
ip link set rtr2net1 netns rtr2

# Add interfaces to net2, move them to their nemaspaces
ip link add link net2 dev rtr1net2 type macvlan mode bridge
ip link set rtr1net2 netns rtr1
ip link add link net2 dev rtr2net2 type macvlan mode bridge
ip link set rtr2net2 netns rtr2

# Add interfaces to net3, move them to their nemaspaces
ip link add link net3 dev rtr2net3 type macvlan mode bridge
ip link set rtr2net3 netns rtr2
ip link add link net3 dev host2net3 type macvlan mode bridge
ip link set host2net3 netns host2

# Configure interfaces and routes in host1
ip netns exec host1 ip link set lo up
ip netns exec host1 ip link set host1net1 up
ip netns exec host1 ip -6 addr add 2000:101::3/64 dev host1net1
ip netns exec host1 ip -6 route add default via 2000:101::1

# Configure interfaces and routes in rtr1
ip netns exec rtr1 ip link set lo up
ip netns exec rtr1 ip link set rtr1net1 up
ip netns exec rtr1 ip -6 addr add 2000:101::1/64 dev rtr1net1
ip netns exec rtr1 ip link set rtr1net2 up
ip netns exec rtr1 ip -6 addr add 2000:102::1/64 dev rtr1net2
ip netns exec rtr1 ip -6 route add default via 2000:102::2
ip netns exec rtr1 sysctl net.ipv6.conf.all.forwarding=1

# Configure interfaces and routes in rtr2
ip netns exec rtr2 ip link set lo up
ip netns exec rtr2 ip link set rtr2net1 up
ip netns exec rtr2 ip -6 addr add 2000:101::2/64 dev rtr2net1
ip netns exec rtr2 ip link set rtr2net2 up
ip netns exec rtr2 ip -6 addr add 2000:102::2/64 dev rtr2net2
ip netns exec rtr2 ip link set rtr2net3 up
ip netns exec rtr2 ip -6 addr add 2000:103::2/64 dev rtr2net3
ip netns exec rtr2 sysctl net.ipv6.conf.all.forwarding=1

# Configure interfaces and routes in host2
ip netns exec host2 ip link set lo up
ip netns exec host2 ip link set host2net3 up
ip netns exec host2 ip -6 addr add 2000:103::4/64 dev host2net3
ip netns exec host2 ip -6 route add default via 2000:103::2

# Ping host2 from host1
ip netns exec host1 ping6 -c5 2000:103::4

# Traceroute host2 from host1
ip netns exec host1 traceroute6 2000:103::4

# Delete nets
ip link del net3
ip link del net2
ip link del net1

# Delete namespaces
ip netns del rtr2
ip netns del rtr1
ip netns del host2
ip netns del host1

Signed-off-by: Francesco Ruggeri <fruggeri@arista.com>
Original-patch-by: Honggang Xu <hxu@arista.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:26:53 -08:00
Olof Johansson
f5ed5010df ARM: tegra: Core changes for v5.5-rc1
Contains two fixes for CPU idle and suspend/resume on early Tegra SoCs.
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Merge tag 'tegra-for-5.5-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

ARM: tegra: Core changes for v5.5-rc1

Contains two fixes for CPU idle and suspend/resume on early Tegra SoCs.

* tag 'tegra-for-5.5-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Use WFE for power-gating on Tegra30
  ARM: tegra: Fix FLOW_CTLR_HALT register clobbering by tegra_resume()

Link: https://lore.kernel.org/r/20191102144521.3863321-5-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:26:33 -08:00
Tuong Lien
06e7c70c6e tipc: improve message bundling algorithm
As mentioned in commit e95584a889 ("tipc: fix unlimited bundling of
small messages"), the current message bundling algorithm is inefficient
that can generate bundles of only one payload message, that causes
unnecessary overheads for both the sender and receiver.

This commit re-designs the 'tipc_msg_make_bundle()' function (now named
as 'tipc_msg_try_bundle()'), so that when a message comes at the first
place, we will just check & keep a reference to it if the message is
suitable for bundling. The message buffer will be put into the link
backlog queue and processed as normal. Later on, when another one comes
we will make a bundle with the first message if possible and so on...
This way, a bundle if really needed will always consist of at least two
payload messages. Otherwise, we let the first buffer go its way without
any need of bundling, so reduce the overheads to zero.

Moreover, since now we have both the messages in hand, we can even
optimize the 'tipc_msg_bundle()' function, make bundle of a very large
(size ~ MSS) and small messages which is not with the current algorithm
e.g. [1400-byte message] + [10-byte message] (MTU = 1500).

Acked-by: Ying Xue <ying.xue@windreiver.com>
Acked-by: Jon Maloy <jon.maloy@ericsson.com>
Signed-off-by: Tuong Lien <tuong.t.lien@dektech.com.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:26:15 -08:00
Olof Johansson
b4067b1050 soc/tegra: Changes for v5.5-rc1
Adds wake event support on Tegra210, implements the NVMEM API for the
 Tegra FUSE block and adds coupled regulators support for Tegra20 and
 Tegra30.
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Merge tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc/tegra: Changes for v5.5-rc1

Adds wake event support on Tegra210, implements the NVMEM API for the
Tegra FUSE block and adds coupled regulators support for Tegra20 and
Tegra30.

* tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Remove unnecessary memory barrier
  soc/tegra: pmc: Query PCLK clock rate at probe time
  soc/tegra: regulators: Add regulators coupler for Tegra30
  soc/tegra: regulators: Add regulators coupler for Tegra20
  soc/tegra: pmc: Configure deep sleep control settings
  soc/tegra: pmc: Configure core power request polarity
  soc/tegra: pmc: Add wake event support on Tegra210
  soc/tegra: pmc: Support wake events on more Tegra SoCs
  soc/tegra: fuse: Register cell lookups for compatibility
  soc/tegra: fuse: Add cell information
  soc/tegra: fuse: Implement nvmem device
  soc/tegra: fuse: Restore base on sysfs failure
  soc/tegra: pmc: Fix crashes for hierarchical interrupts
  soc/tegra: fuse: Add FUSE clock check in tegra_fuse_readl()

Link: https://lore.kernel.org/r/20191102144521.3863321-4-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:25:46 -08:00
Francesco Ruggeri
2adf81c0f7 net: icmp: use input address in traceroute
Even with icmp_errors_use_inbound_ifaddr set, traceroute returns the
primary address of the interface the packet was received on, even if
the path goes through a secondary address. In the example:

                    1.0.3.1/24
 ---- 1.0.1.3/24    1.0.1.1/24 ---- 1.0.2.1/24    1.0.2.4/24 ----
 |H1|--------------------------|R1|--------------------------|H2|
 ----            N1            ----            N2            ----

where 1.0.3.1/24 is R1's primary address on N1, traceroute from
H1 to H2 returns:

traceroute to 1.0.2.4 (1.0.2.4), 30 hops max, 60 byte packets
 1  1.0.3.1 (1.0.3.1)  0.018 ms  0.006 ms  0.006 ms
 2  1.0.2.4 (1.0.2.4)  0.021 ms  0.007 ms  0.007 ms

After applying this patch, it returns:

traceroute to 1.0.2.4 (1.0.2.4), 30 hops max, 60 byte packets
 1  1.0.1.1 (1.0.1.1)  0.033 ms  0.007 ms  0.006 ms
 2  1.0.2.4 (1.0.2.4)  0.011 ms  0.007 ms  0.007 ms

Original-patch-by: Bill Fenner <fenner@arista.com>
Signed-off-by: Francesco Ruggeri <fruggeri@arista.com>
Reviewed-by: David Ahern <dsahern@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:25:18 -08:00
Marcel Ziswiler
a5c959ef99 dt-bindings: arm: fsl: add nxp based toradex colibri-imx8x bindings
Document the NXP SoC based Toradex Colibri iMX8X module and carrier
board devicetree bindings previously added.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-04 09:24:00 +08:00
Marcel Ziswiler
0bfadbcdc7 dt-bindings: arm: fsl: add nxp based toradex apalis/colibri bindings
Document the following NXP SoC based Toradex Apalis and Colibri module
and carrier board devicetree bindings already supported:
- toradex,apalis_imx6q            # Apalis iMX6 Module
- toradex,apalis_imx6q-eval       # Apalis iMX6 Module on Apalisi
				    Evaluation Board
- toradex,apalis_imx6q-ixora      # Apalis iMX6 Module on Ixora
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1

- toradex,colibri_imx6dl          # Colibri iMX6 Module
- toradex,colibri_imx6dl-eval-v3  # Colibri iMX6 Module on Colibri
				    Evaluation Board V3

- toradex,colibri-imx6ull-eval            # Colibri iMX6ULL Module on
					    Colibri Evaluation Board
- toradex,colibri-imx6ull-wifi-eval       # Colibri iMX6ULL Wi-Fi /
					    Bluetooth Module on Colibri
					    Evaluation Board

- toradex,colibri-imx7s           # Colibri iMX7 Solo Module
- toradex,colibri-imx7s-eval-v3   # Colibri iMX7 Solo Module on
				    Colibri Evaluation Board V3

- toradex,colibri-imx7d                   # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-emmc              # Colibri iMX7 Dual 1GB (eMMC)
					    Module
- toradex,colibri-imx7d-emmc-eval-v3      # Colibri iMX7 Dual 1GB (eMMC)
                                            Module on Colibri Evaluation
					    Board V3
- toradex,colibri-imx7d-eval-v3           # Colibri iMX7 Dual Module on
					    Colibri Evaluation Board V3
- toradex,vf500-colibri_vf50              # Colibri VF50 Module
- toradex,vf500-colibri_vf50-on-eval      # Colibri VF50 Module on
					    Colibri Evaluation Board
- toradex,vf610-colibri_vf61              # Colibri VF61 Module
- toradex,vf610-colibri_vf61-on-eval      # Colibri VF61 Module on
					    Colibri Evaluation Board

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-04 09:23:18 +08:00
Olof Johansson
f76b6a4cbf firmware: tegra: Changes for v5.5-rc1
This contains a single fix for suspend/resume on Tegra194.
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Merge tag 'tegra-for-5.5-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

firmware: tegra: Changes for v5.5-rc1

This contains a single fix for suspend/resume on Tegra194.

* tag 'tegra-for-5.5-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  firmware: tegra: Move BPMP resume to noirq phase

Link: https://lore.kernel.org/r/20191102144521.3863321-2-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:19:50 -08:00
Olof Johansson
c267d9960c dt-bindings: Changes for v5.5-rc1
This contains various updates to device tree bindings and includes that
 are related to driver changes in other Tegra branches.
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Merge tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.5-rc1

This contains various updates to device tree bindings and includes that
are related to driver changes in other Tegra branches.

* tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller
  dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
  dt-bindings: memory: tegra30: Convert to Tegra124 YAML
  dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs
  dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT

Link: https://lore.kernel.org/r/20191102144521.3863321-1-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:19:28 -08:00
David S. Miller
c219a16622 Merge branch 'optimize-openvswitch-flow-looking-up'
Tonghao Zhang says:

====================
optimize openvswitch flow looking up

This series patch optimize openvswitch for performance or simplify
codes.

Patch 1, 2, 4: Port Pravin B Shelar patches to
linux upstream with little changes.

Patch 5, 6, 7: Optimize the flow looking up and
simplify the flow hash.

Patch 8, 9: are bugfix.

The performance test is on Intel Xeon E5-2630 v4.
The test topology is show as below:

+-----------------------------------+
|   +---------------------------+   |
|   | eth0   ovs-switch    eth1 |   | Host0
|   +---------------------------+   |
+-----------------------------------+
      ^                       |
      |                       |
      |                       |
      |                       |
      |                       v
+-----+----+             +----+-----+
| netperf  | Host1       | netserver| Host2
+----------+             +----------+

We use netperf send the 64B packets, and insert 255+ flow-mask:
$ ovs-dpctl add-flow ovs-switch "in_port(1),eth(dst=00:01:00:00:00:00/ff:ff:ff:ff:ff:01),eth_type(0x0800),ipv4(frag=no)" 2
...
$ ovs-dpctl add-flow ovs-switch "in_port(1),eth(dst=00:ff:00:00:00:00/ff:ff:ff:ff:ff:ff),eth_type(0x0800),ipv4(frag=no)" 2
$
$ netperf -t UDP_STREAM -H 2.2.2.200 -l 40 -- -m 18

* Without series patch, throughput 8.28Mbps
* With series patch, throughput 46.05Mbps

v6:
some coding style fixes

v5:
rewrite patch 8, release flow-mask when freeing flow

v4:
access ma->count with READ_ONCE/WRITE_ONCE API. More information,
see patch 5 comments.

v3:
update ma point when realloc mask_array in patch 5

v2:
simplify codes. e.g. use kfree_rcu instead of call_rcu
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:04 -08:00
Tonghao Zhang
eec62eadd1 net: openvswitch: simplify the ovs_dp_cmd_new
use the specified functions to init resource.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:04 -08:00
Tonghao Zhang
4c76bf696a net: openvswitch: don't unlock mutex when changing the user_features fails
Unlocking of a not locked mutex is not allowed.
Other kernel thread may be in critical section while
we unlock it because of setting user_feature fail.

Fixes: 95a7233c4 ("net: openvswitch: Set OvS recirc_id from tc chain index")
Cc: Paul Blakey <paulb@mellanox.com>
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: William Tu <u9012063@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:04 -08:00
Tonghao Zhang
50b0e61b32 net: openvswitch: fix possible memleak on destroy flow-table
When we destroy the flow tables which may contain the flow_mask,
so release the flow mask struct.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
0a3e01371d net: openvswitch: add likely in flow_lookup
The most case *index < ma->max, and flow-mask is not NULL.
We add un/likely for performance.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: William Tu <u9012063@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
515b65a4b9 net: openvswitch: simplify the flow_hash
Simplify the code and remove the unnecessary BUILD_BUG_ON.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: William Tu <u9012063@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
57f7d7b916 net: openvswitch: optimize flow-mask looking up
The full looking up on flow table traverses all mask array.
If mask-array is too large, the number of invalid flow-mask
increase, performance will be drop.

One bad case, for example: M means flow-mask is valid and NULL
of flow-mask means deleted.

+-------------------------------------------+
| M | NULL | ...                  | NULL | M|
+-------------------------------------------+

In that case, without this patch, openvswitch will traverses all
mask array, because there will be one flow-mask in the tail. This
patch changes the way of flow-mask inserting and deleting, and the
mask array will be keep as below: there is not a NULL hole. In the
fast path, we can "break" "for" (not "continue") in flow_lookup
when we get a NULL flow-mask.

         "break"
            v
+-------------------------------------------+
| M | M |  NULL |...           | NULL | NULL|
+-------------------------------------------+

This patch don't optimize slow or control path, still using ma->max
to traverse. Slow path:
* tbl_mask_array_realloc
* ovs_flow_tbl_lookup_exact
* flow_mask_find

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
a7f35e78e7 net: openvswitch: optimize flow mask cache hash collision
Port the codes to linux upstream and with little changes.

Pravin B Shelar, says:
| In case hash collision on mask cache, OVS does extra flow
| lookup. Following patch avoid it.

Link: 0e6efbe271
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Signed-off-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
1689754de6 net: openvswitch: shrink the mask array if necessary
When creating and inserting flow-mask, if there is no available
flow-mask, we realloc the mask array. When removing flow-mask,
if necessary, we shrink mask array.

Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: William Tu <u9012063@gmail.com>
Acked-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
4bc63b1b53 net: openvswitch: convert mask list in mask array
Port the codes to linux upstream and with little changes.

Pravin B Shelar, says:
| mask caches index of mask in mask_list. On packet recv OVS
| need to traverse mask-list to get cached mask. Therefore array
| is better for retrieving cached mask. This also allows better
| cache replacement algorithm by directly checking mask's existence.

Link: d49fc3ff53
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: William Tu <u9012063@gmail.com>
Signed-off-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Tonghao Zhang
04b7d136d0 net: openvswitch: add flow-mask cache for performance
The idea of this optimization comes from a patch which
is committed in 2014, openvswitch community. The author
is Pravin B Shelar. In order to get high performance, I
implement it again. Later patches will use it.

Pravin B Shelar, says:
| On every packet OVS needs to lookup flow-table with every
| mask until it finds a match. The packet flow-key is first
| masked with mask in the list and then the masked key is
| looked up in flow-table. Therefore number of masks can
| affect packet processing performance.

Link: 5604935e4e
Signed-off-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Tested-by: Greg Rose <gvrose8192@gmail.com>
Acked-by: William Tu <u9012063@gmail.com>
Signed-off-by: Pravin B Shelar <pshelar@ovn.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-11-03 17:18:03 -08:00
Peng Fan
bceed71ba1 clk: imx: imx8mq: fix sys3_pll_out_sels
It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.

According to the current imx_clk_sccg_pll design, it uses both
bypass1/2, however set bypass2 as 1 is not correct, because it will
make sys[x]_pll_out use wrong parent and might access wrong registers.

So correct bypass2 to 0 and fix sys3_pll_out_sels.

Fixes: e9dda4af68 ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-04 09:10:49 +08:00
Olof Johansson
fcdc437224 One new patch to the arm64 defconfig to enable the new crypto engine
driver.
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Merge tag 'sunxi-config64-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig

One new patch to the arm64 defconfig to enable the new crypto engine
driver.

* tag 'sunxi-config64-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: defconfig: add new Allwinner crypto options

Link: https://lore.kernel.org/r/539241d6-9b2e-4d5b-bd63-f912cf6ebf96.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:08:26 -08:00
Olof Johansson
5003119e43 Two new drivers enabled in sunxi_defconfig: one for the PHY found on
multiple boards, one for the new crypto driver.
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Merge tag 'sunxi-config-for-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig

Two new drivers enabled in sunxi_defconfig: one for the PHY found on
multiple boards, one for the new crypto driver.

* tag 'sunxi-config-for-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: configs: sunxi: Enable MICREL_PHY
  ARM: configs: sunxi: add new Allwinner crypto options

Link: https://lore.kernel.org/r/27125172-7ce8-427e-83f9-8e9bd69d50a4.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:08:10 -08:00
Olof Johansson
42a5718b8c Our usual bunch of DT patches, with this time mostly:
- Mali GPU support for the H6
  - Two new crypto drivers enablement
  - A few fixes to our DTs, fixed through the validation effort
  - New boards: NanoPi Duo2
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Merge tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Our usual bunch of DT patches, with this time mostly:
 - Mali GPU support for the H6
 - Two new crypto drivers enablement
 - A few fixes to our DTs, fixed through the validation effort
 - New boards: NanoPi Duo2

* tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits)
  dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2
  ARM: dts: sun8i: add FriendlyARM NanoPi Duo2
  arm64: allwinner: h6: Enable GPU node for Tanix TX6
  arm64: dts: allwinner: bluetooth for Emlid Neutis N5
  ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins
  ARM: dts: sun9i: a80: Add Security System node
  ARM: dts: sun8i: a83t: Add Security System node
  arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6
  arm64: dts: allwinner: sun50i: Add crypto engine node on H5
  arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64
  ARM: dts: sun8i: H3: Add Crypto Engine node
  ARM: dts: sun8i: R40: add crypto engine node
  dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
  arm64: dts: allwinner: Add mali GPU supply for H6 boards
  arm64: dts: allwinner: Add ARM Mali GPU node for H6
  ARM: dts: sun8i: a83t: a711: Add touchscreen node
  ARM: dts: sun5i: olinuxino micro: Fix AT24 node name
  ARM: dts: sun9i: Add missing watchdog clocks
  arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3
  arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth
  ...

Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:07:52 -08:00
Geert Uytterhoeven
f638b287cc ARM: dts: atlas7: Fix "debounce-interval" property misspelling
"debounce_interval" was never supported.

Link: https://lore.kernel.org/r/20191101160356.32034-3-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:06:55 -08:00
Geert Uytterhoeven
09612c9337 arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/
The standard DT property is called "#interrupt-cells".

Link: https://lore.kernel.org/r/20191101160356.32034-2-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:06:43 -08:00
Geert Uytterhoeven
9e3bd0f664 arm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/
The standard DT property is called "#interrupt-cells".

Link: https://lore.kernel.org/r/20191101160356.32034-1-geert+renesas@glider.be
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:06:33 -08:00
Olof Johansson
b23c30a955 Renesas DT binding updates for v5.5 (take two)
- JSON schema conversion,
   - Core support for the new R-Car M3-W+ (r8a77961) SoC,
   - Board compatible updates.
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Merge tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas DT binding updates for v5.5 (take two)

  - JSON schema conversion,
  - Core support for the new R-Car M3-W+ (r8a77961) SoC,
  - Board compatible updates.

* tag 'renesas-dt-bindings-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  dt-bindings: power: rcar-sysc: Document r8a77961 support
  dt-bindings: reset: rcar-rst: Document r8a77961 support
  dt-bindings: arm: renesas: Add Salvator-XS board with R-Car M3-W+
  dt-bindings: arm: renesas: Document R-Car M3-W+ SoC DT bindings
  dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher
  dt-bindings: arm: renesas: Convert 'renesas,prr' to json-schema

Link: https://lore.kernel.org/r/20191101155842.31467-7-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:06:11 -08:00
Olof Johansson
064652ad88 Renesas driver updates for v5.5 (take two)
- Initial support for the R-Car M3-W+ (r8a77961) SoC,
   - A minor fix.
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Merge tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.5 (take two)

  - Initial support for the R-Car M3-W+ (r8a77961) SoC,
  - A minor fix.

* tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-sysc: Add R8A77961 support
  soc: renesas: rcar-rst: Add R8A77961 support
  soc: renesas: Identify R-Car M3-W+
  soc: renesas: Add ARCH_R8A77961 for new R-Car M3-W+
  soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W
  soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960
  soc: renesas: Add missing check for non-zero product register address
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions

Link: https://lore.kernel.org/r/20191101155842.31467-6-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:05:46 -08:00
Olof Johansson
571d32c283 Renesas ARM64 DT updates for v5.5 (take two)
- Video-Input and Serial-ATA support on RZ/G2N,
   - Color Management Module support on various R-Car Gen3 SoCs,
   - Initial support for the R-Car M3-W+ (r8a77961) SoC on the
     Salvator-XS board.
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Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.5 (take two)

  - Video-Input and Serial-ATA support on RZ/G2N,
  - Color Management Module support on various R-Car Gen3 SoCs,
  - Initial support for the R-Car M3-W+ (r8a77961) SoC on the
    Salvator-XS board.

* tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+
  arm64: dts: renesas: Add Renesas R8A77961 SoC support
  arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions
  arm64: dts: renesas: r8a774b1: Add SATA controller node
  arm64: dts: renesas: rcar-gen3: Add CMM units
  arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support

Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:05:19 -08:00
Olof Johansson
4075e0db48 Renesas ARM64 defconfig updates for v5.5 (take two)
- Enable support for the new R-Car M3-W+ (r8a77961) SoC.
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Merge tag 'renesas-arm64-defconfig-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig

Renesas ARM64 defconfig updates for v5.5 (take two)

  - Enable support for the new R-Car M3-W+ (r8a77961) SoC.

* tag 'renesas-arm64-defconfig-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: defconfig: Enable R8A77961 SoC

Link: https://lore.kernel.org/r/20191101155842.31467-4-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:04:38 -08:00
Olof Johansson
3bd00db6f0 Renesas ARM SoC updates for v5.5
- Drop legacy DT clock support on R-Car Gen2.
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Merge tag 'renesas-arm-soc-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc

Renesas ARM SoC updates for v5.5

  - Drop legacy DT clock support on R-Car Gen2.

* tag 'renesas-arm-soc-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: shmobile: rcar-gen2: Drop legacy DT clock support

Link: https://lore.kernel.org/r/20191101155842.31467-3-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:04:18 -08:00
Olof Johansson
9a67a6ec9f Renesas ARM defconfig updates for v5.5
- Refresh shmobile_defconfig for v5.4-rc1.
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Merge tag 'renesas-arm-defconfig-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/defconfig

Renesas ARM defconfig updates for v5.5

  - Refresh shmobile_defconfig for v5.4-rc1.

* tag 'renesas-arm-defconfig-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: shmobile: defconfig: Refresh for v5.4-rc1

Link: https://lore.kernel.org/r/20191101155842.31467-2-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:03:55 -08:00
Olof Johansson
19e489aa9b PRM reset control dts changes for v5.5 merge window
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
 and dra7 SoCs. The reset driver changes make it easier to add support for
 various accelerators for TI SoCs in a more generic way.
 
 Note that this branch is based on the PRM reset driver changes branch.
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Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

PRM reset control dts changes for v5.5 merge window

This series of changes adds the PRM reset driver nodes for am3/4, omap4/5
and dra7 SoCs. The reset driver changes make it easier to add support for
various accelerators for TI SoCs in a more generic way.

Note that this branch is based on the PRM reset driver changes branch.

* tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: omap5: Add PRM data
  ARM: dts: am43xx: Add PRM data
  ARM: dts: am33xx: Add PRM data
  ARM: dts: omap4: add PRM nodes
  ARM: dts: dra7: add PRM nodes
  soc: ti: omap-prm: add omap5 PRM data
  soc: ti: omap-prm: add am4 PRM data
  soc: ti: omap-prm: add dra7 PRM data
  soc: ti: omap-prm: add data for am33xx
  soc: ti: omap-prm: add omap4 PRM data
  soc: ti: omap-prm: add support for denying idle for reset clockdomain
  soc: ti: omap-prm: poll for reset complete during de-assert
  soc: ti: add initial PRM driver with reset control support
  dt-bindings: omap: add new binding for PRM instances

Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:02:07 -08:00
Lubomir Rintel
7e6a303179 ARM: dts: mmp3-dell-ariel: Add a serial point alias
Make sure UART3, where the console is, is called ttyS2. That is
consistent with the early console.

Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:01:01 -08:00
Lubomir Rintel
75ebe3bce0 ARM: dts: mmp3-dell-ariel: Add a name to /memory node
Ponted out by DTC:

  <stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges
  property, but no unit name

Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:00:44 -08:00
Lubomir Rintel
d074a263dd ARM: dts: mmp3: Fix /soc/watchdog node name
There's a typo there that rightfully upsets DTS:

  <stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus
  unit address format error, expected "e0000620"

Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:00:37 -08:00
Lubomir Rintel
302417ce98 ARM: dts: mmp3: Add a name to /clocks node
It should have one and DTC is indeed unhappy about its absence:

  <stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or
  ranges property, but no unit name

Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:00:28 -08:00
Tao Ren
a3ee4fea24 ARM: ASPEED: update default ARCH_NR_GPIO for ARCH_ASPEED
Increase the max number of GPIOs from default 512 to 1024 for ASPEED
platforms, because Facebook Yamp (AST2500) BMC platform has total 594
GPIO pins (232 provided by ASPEED SoC, and 362 by I/O Expanders).

Link: https://lore.kernel.org/r/20191031014040.12898-1-rentao.bupt@gmail.com
Signed-off-by: Tao Ren <rentao.bupt@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 17:00:07 -08:00
Manivannan Sadhasivam
9fe2420d06 ARM: dts: Add RDA8810PL GPIO controllers
Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers
in this SoC with maximum of 32 gpios. Except GPIOC, all controllers
are capable of generating edge/level interrupts from first 8 lines.

Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:59:28 -08:00
Olof Johansson
ae314d78b5 ARM64: hisilicon: defconfig updates for 5.5
- enable ARM SMMUv3 PMU and hisi ZIP controller as module for
   Kunpeng920 SoC
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Merge tag 'hisi-arm64-defconfig-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/defconfig

ARM64: hisilicon: defconfig updates for 5.5

- enable ARM SMMUv3 PMU and hisi ZIP controller as module for
  Kunpeng920 SoC

* tag 'hisi-arm64-defconfig-for-5.5' of git://github.com/hisilicon/linux-hisi:
  arm64: defconfig: Enable SMMU v3 PMCG
  arm64: defconfig: Enable HiSilicon ZIP controller

Link: https://lore.kernel.org/r/5DB95B1E.8060607@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:56:44 -08:00
Olof Johansson
32f714d30f ARM64: DT: Hisilicon SoCs DT updates for 5.5
- add Mali450 MP4 GPU node in the hi6220 SoC
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Merge tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM64: DT: Hisilicon SoCs DT updates for 5.5

- add Mali450 MP4 GPU node in the hi6220 SoC

* tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry

Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:56:25 -08:00
Olof Johansson
a9f4b135d1 ARM: mach-hisi: Hisilicon SoC updates for 5.5
- drop the ARCH_MULTI_V7 dependency in the sub-menu of ARCH_HISI
   since ARCH_HISI depends on ARCH_MULTI_V7
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Merge tag 'hisi-armv7-soc-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/soc

ARM: mach-hisi: Hisilicon SoC updates for 5.5

- drop the ARCH_MULTI_V7 dependency in the sub-menu of ARCH_HISI
  since ARCH_HISI depends on ARCH_MULTI_V7

* tag 'hisi-armv7-soc-for-5.5' of git://github.com/hisilicon/linux-hisi:
  ARM: hisi: drop useless depend on ARCH_MULTI_V7

Link: https://lore.kernel.org/r/5DB9593D.9050904@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:55:17 -08:00
Olof Johansson
a1094a7c27 Realtek ARM64 based SoC DT for v5.5
Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
 Add reset controllers for RTD129x and start using them for UARTs.
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Merge tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt

Realtek ARM64 based SoC DT for v5.5

Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
Add reset controllers for RTD129x and start using them for UARTs.

* tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
  arm64: dts: realtek: Add RTD129x UART resets
  arm64: dts: realtek: Add RTD129x reset controller nodes
  dt-bindings: reset: Add Realtek RTD1295
  arm64: dts: realtek: Add watchdog node for RTD129x
  arm64: dts: realtek: Add oscillator for RTD129x
  arm64: dts: realtek: Add RTD1296 and Synology DS418
  dt-bindings: arm: realtek: Document RTD1296 and Synology DS418
  arm64: dts: realtek: Add RTD1293 and Synology DS418j
  arm64: dts: realtek: Change dual-license from MIT to BSD
  dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j
  dt-bindings: arm: realtek: Tidy up conversion to json-schema

Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:54:33 -08:00
Olof Johansson
433b1e8a6c Realtek ARM64 based SoC for v5.5
Enable reset controllers and add a mailing list to MAINTAINERS.
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Merge tag 'realtek-arm64-soc-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/soc

Realtek ARM64 based SoC for v5.5

Enable reset controllers and add a mailing list to MAINTAINERS.

* tag 'realtek-arm64-soc-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
  arm64: realtek: Select reset controller
  MAINTAINERS: Add mailing list for Realtek SoCs

Link: https://lore.kernel.org/r/20191030041000.31848-1-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:54:07 -08:00
Olof Johansson
4454c069f1 Merge branch 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/dt
* 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  ARM: configs: keystone: enable cpts
  ARM: dts: k2l-netcp: add cpts refclk_mux node
  ARM: dts: k2hk-netcp: add cpts refclk_mux node
  ARM: dts: k2e-netcp: add cpts refclk_mux node
  ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b
  ARM: dts: keystone-clocks: add input fixed clocks

Link: https://lore.kernel.org/r/1572372856-20598-2-git-send-email-santosh.shilimkar@oracle.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:53:38 -08:00
Olof Johansson
e6ce7f5a7d Merge branch 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers
* 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs'
  soc: ti: omap-prm: fix return value check in omap_prm_probe()
  soc: ti: omap-prm: add omap5 PRM data
  soc: ti: omap-prm: add am4 PRM data
  soc: ti: omap-prm: add dra7 PRM data
  soc: ti: omap-prm: add data for am33xx
  soc: ti: omap-prm: add omap4 PRM data
  soc: ti: omap-prm: add support for denying idle for reset clockdomain
  soc: ti: omap-prm: poll for reset complete during de-assert
  soc: ti: add initial PRM driver with reset control support
  dt-bindings: omap: add new binding for PRM instances

Link: https://lore.kernel.org/r/1572372856-20598-1-git-send-email-santosh.shilimkar@oracle.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-11-03 16:53:08 -08:00
Fabio Estevam
0b68096308 arm64: dts: ls1028a: Fix tmu unit address
The following build warning is seen with W=1:

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:531.20-581.5: Warning (simple_bus_reg): /soc/tmu@1f00000: simple-bus unit address format error, expected "1f80000"

Fix it by adjusting the tmu unit address to match its reg entry.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-04 08:52:14 +08:00
Fabio Estevam
68e36a429e arm64: dts: ls1028a: Move thermal-zone out of SoC
Move thermal-zone node from the soc node to the root node.

thermal-zone node does not have any register properties and thus
shouldn't be placed on the bus.

This fixes the following build warnings with W=1:

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:583.17-612.5: Warning (simple_bus_reg): /soc/thermal-zones: missing or empty reg/ranges property

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-11-04 08:52:14 +08:00