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linux/drivers/soc/tegra
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Aaron Kling 020ecb16e5 soc/tegra: fuse: speedo-tegra210: Update speedo IDs 
[ Upstream commit ce27c9c212 ]

Existing code only sets CPU and GPU speedo IDs 0 and 1. The CPU DVFS
code supports 11 IDs and nouveau supports 5. This aligns with what the
downstream vendor kernel supports. Align SKUs with the downstream list.

The Tegra210 CVB tables were added in the first referenced fixes commit.
Since then, all Tegra210 SoCs have tried to scale to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.

Fixes: 2b2dbc2f94 ("clk: tegra: dfll: add CVB tables for Tegra210")
Fixes: 579db6e5d9 ("arm64: tegra: Enable DFLL support on Jetson Nano")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2025-12-18 14:03:01 +01:00
..
cbb soc/tegra: cbb: Add support for CBB fabrics in Tegra254 2025-07-09 14:29:19 +02:00
fuse soc/tegra: fuse: speedo-tegra210: Update speedo IDs 2025-12-18 14:03:01 +01:00
ari-tegra186.c soc/tegra: Add Tegra186 ARI driver 2021-10-08 21:42:38 +02:00
common.c soc/tegra: Migrate to dev_pm_opp_set_config() 2022-07-08 11:27:33 +05:30
flowctrl.c soc/tegra: flowctrl: Use devm_platform_get_and_ioremap_resource() 2023-04-05 14:59:09 +02:00
Kconfig pinctrl: tegra: Add Tegra186 pinmux driver 2025-08-19 13:26:51 +02:00
Makefile soc: tegra: Move powergate-bpmp driver to the genpd dir 2023-07-14 10:40:56 +02:00
pmc.c soc/tegra: pmc: Ensure power-domains are in a known state 2025-08-11 12:24:43 +02:00
regulators-tegra20.c soc/tegra: regulators: Prepare for suspend 2021-12-16 14:03:38 +01:00
regulators-tegra30.c soc/tegra: regulators: Prepare for suspend 2021-12-16 14:03:38 +01:00