Commit graph

1,467,710 commits

Author SHA1 Message Date
Shiwu Zhang
188edb8a62 drm/amdgpu: retire rb settings from gfx v12.1.0
Use the default all zero settings.

Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:42:04 -04:00
Hawking Zhang
e022d7f631 drm/amdgpu/mmhub_v4_2: Remove obsolete programming
The underlying functionality was removed

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:42:01 -04:00
Hawking Zhang
2ed2adcdbb drm/amdgpu/gfxhub_v12_1: Remove obsolete programming
The underlying functionality was removed

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:59 -04:00
Alex Sierra
2d9a33154a drm/amdgpu: fix master_xcc_ids[] indexing for non-zero xcc_id
add_hw_queue, remove_hw_queue, set_hw_resources_1 and inv_tlbs_pasid
read master_xcc_ids[MES_PIPE_INST(xcc_id, SCHED)]. That only worked
for xcc_id == 0; with a non-zero target (e.g. partition-1 master in
DPX) it read an uninitialised slot. Index by xcc_id consistently, and
fix the related shared_cmd_buf_gpu_addr[] index in
set_hw_resources_1() to use MES_PIPE_INST(master_xcc_id, pipe).
All indexing stays in logical XCC space, so this remains correct with
harvested XCCs; the existing ip_map / GET_INST() translation handles
the logical-to-physical conversion at the HW register boundary.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:56 -04:00
Le Ma
5e23e92af2 drm/amdgpu: skip xgmi operations for non-xgmi multi-node configs
On multi-node configurations without XGMI interconnect (e.g. A+A),
num_physical_nodes can be greater than 1 even though XGMI is not supported.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:54 -04:00
Lijo Lazar
6028808e37 drm/amdgpu: Use partition switch shadow register
Control register is access restricted. Use the read-only copy to read
the partition settings.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:52 -04:00
Mangesh Gadre
ae6552ed04 drm/amdgpu: Updated compute partition validation
DPX is only valid partition mode in NPS2.
Updated check which was making CPX as
available compute partition mode instead of DPX

Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:49 -04:00
Harish Kasiviswanathan
da352ff193 drm/amdkfd: Don't use DEVICE_COHERENT on GFX12.1
NICs attached to remote GPUs are unable to access VRAM coherently.
Hence, use DEVICE_PRIVATE for GFX12.1

v2: Squash in Fix migrate_vma DEVICE_COHERENT setting

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:47 -04:00
Likun Gao
061df6a184 drm/amdgpu: Correct GFX_IMU_PARTITION_SWITCH value for gc 12_1
Correct regGFX_IMU_PARTITION_SWITCH value to suitable for harvest
situation for gfx v12.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Jinzhou Su <jinzhou.su@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:45 -04:00
Hawking Zhang
9a2f2720fb drm/amdgpu: Init partition_mode and xcc_mask for GFX_IMU_PARTITION_SWITCH
Set partition_mode and physical xcc mask fields in
GFX_IMU_PARTITION_SWITCH register

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:43 -04:00
Philip Yang
763b6076a9 drm/amdgpu: LSDMA check PIO error status
Check LSDMA PIO error status bits after each transfer completes to
detect silent copy failures caused by issues such as IFoE (Infinity
Fabric over Ethernet) errors.

The following error conditions are checked:
- Write return NACK / general error
- Read return NACK / general error
- Invalid address
- Zero count
- DRAM ECC error

Log the error via dev_warn() and clear only the set error bits
(write-1-to-clear) so that subsequent transfers can proceed once the
underlying issue is resolved.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:41 -04:00
Philip Yang
a3b523ed4c drm/amdgpu: LSDMA supports multiple threads
Add mutex to serialize LSDMA PIO copy and fill operations for
concurrent access from multiple threads.

A mutex is used rather than a spinlock because the underlying
lsdma_v7_1_wait_pio_status() polls with udelay(), which can
busy-wait for up to usec_timeout microseconds.

It is optional to call mutex_destroy for clarity and debug
correctness, it is no-op for release build, leave it as lsdma
block no ip callback funcs to call mutex_destroy.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:38 -04:00
Mukul Joshi
32e1f992b3 drm/amdkfd: Update SDMA engines reporting for GFX 12.1
On GFX 12.1, all SDMA engines are the same from HW perspective.
As a result, report all SDMA engines as regular/PCIe SDMA engines.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:33 -04:00
Feifei Xu
d75118af05 drm/amdgpu: Disable SDMA Hang WatchDog in SDMA_v7_1
A temporary workaround to unblock usermode tests.
Will revert once issue resolved.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:29 -04:00
Likun Gao
9b42ec82ce drm/amdgpu: add sdma debug parameter
Add parameter to switch sdma RB CMD for sdma v7.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:24 -04:00
Bokun Zhang
4052b52a30 drm/amdgpu: Add JPEG v5.0.2 SRIOV code path
- Add JPEG v5.0.2 SRIOV code path
- Add JPEG MMSCH init table transfer
- Skip unsupported actions such as power gating
  and per queue reset for SRIOV VF.

Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:21 -04:00
Bokun Zhang
98ba50b2ef drm/amdgpu: Add VCN v5.0.2 SRIOV code path
- Add VCN v5.0.2 SRIOV code path
- Add VCN MMSCH init table transfer
- Skip unsupported actions such as power gating
  and per queue reset for SRIOV VF.

Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:18 -04:00
Boyuan Zhang
c111c72c8e drm/amdgpu/jpeg: fix jpeg_v5_0_2_is_idle detection
jpeg_v5_0_2_is_idle() initializes ret to false and then accumulates ring
idle status using &=. Since false & condition always remains false, the
function can never report the JPEG block as idle.

Initialize ret to true so the function returns true only when all JPEG
rings report RB_JOB_DONE.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:16 -04:00
Hawking Zhang
7b20077158 drm/amd/display: use GNU make rwildcard instead of find
Replace external find calls with GNU Make’s $(rwildcard …)
to collect files. Depending on ‘find’ can fail if it’s
unavailable or returns no matches, which left CFLAGS_*
unset. In that case, floating-point code was built
with -mno-sse, leading to build failures.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:14 -04:00
Xiang Liu
0ce46e5478 drm/amd/ras: record the fatal state on every device of the hive
The fatal error interrupt is broadcast to every device of the hive and
they all race for amdgpu_ras_global_ras_isr(), which hands -EBUSY to
everyone but the winner. Treating that as a failure returns before the
device is marked, so seven devices out of eight are left without their
fatal and SRAM ECC state, the one that actually logged the error among
them. KFD then tells the processes on those devices that the reset was
a plain hang.

-EBUSY only means the reset has already been asked for. Record the
state anyway and leave the request to the winner.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:11 -04:00
Xiang Liu
61ed5cff46 drm/amd/ras: tell KFD the reset came from an ECC error
kfd_signal_reset_event() picks between KFD_HW_EXCEPTION_ECC and
KFD_HW_EXCEPTION_GPU_HANG from the SRAM ECC flag, and only delivers the
memory exception event for the former. Nothing raises that flag on the
RAS module paths, so a reset caused by an uncorrectable or a consumed
poison error is reported to every process on the device as a plain hang
and the runtime carries on instead of tearing the workload down.

Raise it the way the per IP callbacks used to.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:09 -04:00
Xiang Liu
dc2c4219ea drm/amd/ras: drop the RAS module state when its sw init fails
The failure paths free the RAS manager but keep the flags that advertise
it as the owner of RAS and of the RAS firmware load. Every entry point
gated on those hits the NULL manager, hw_init turns that into -EINVAL
and the whole probe fails.

Clear both once the manager is gone, and route the allocation failure
through the same place.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:07 -04:00
Xiang Liu
1034640cbd drm/amd/ras: tolerate an unsupported MCA debug mode control
ras_mp1_set_debug_mode() reports -EOPNOTSUPP where the control does not
exist, an SR-IOV guest among them. Treating that as fatal fails
ras_core_sw_init() and takes RAS down on every VF.

Nothing else in the MP1 block depends on it, so carry on.

Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:05 -04:00
Amber Lin
7744b653e3 drm/amdgpu: Fix reset_hw_queue on MES 12.1
Different from detect_and_reset, reset_hw_queue performs per queue
reset. Per queue reset setting requires reset_queue_only=1 and hung
queue's doorbell_offset in RESET packet. This packet must be sent to MES
pipe 0(SCHED_PIPE).

We also need to set enable_compute_pipe_reset=1 in SET_HW_RESOURCES so
when queue reset fails, MES will proceed pipe reset.

This patch also fixes a bug in mes_v12_1_reset_hw_queue function. Instead
of using MESAPI__RESET offset for api_status, the existing code uses
MESAPI__REMOVE_QUEUE.

Signed-off-by: Amber Lin <amber.lin@amd.com>
Reviewed-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:41:02 -04:00
Eric Huang
c0431e1aec drm/amdgpu/userq: create the same workaround of oversubscription timer
removing MES oversubscription timer will affect both amdgpu/amdkfd, so
add the similar timer for amdgpu userq as well.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:59 -04:00
Eric Huang
590e266261 drm/amdkfd: workaround 100% gpu usage issue for gfx11
the issue only happens with oversubscription when gpu has no
workload, the root cause is mes oversubscription timer, so
disable mes timer and make a similar timer in kfd to resolve
the issue.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:56 -04:00
Eric Huang
6f04757cfe drm/amdgpu: add new mes misc api for gfx11
new api will be used to workaround a HW scheduler issue
for 100% usage when gpu has no workload.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:54 -04:00
Taimur Hassan
3203fc349a drm/amd/display: Promote DC to 3.2.395
This version brings along the following updates:

 - Fix HPO test regressions.
 - Refactor DPP_SET_INPUT_TRANSFER_FUNC to drop pipe_ctx params.
 - Use fast update path for address-only plane flips.
 - Split OPTC_PIPE_CONTROL_LOCK into smaller helpers.
 - Fix DPREFCLK override when SMU isn't available.
 - Fix CalculateFlipSchedule calculation.
 - Add hook to disable alt-ch in PMO.
 - Update alt-ch size calculations.
 - Enable min dispclk ODM on DCN42.
 - Remove RMCM tetrahedral cube from dc_plane_state.
 - Fix mismatch number of OPP/DPP accounting.
 - Adjust vblank_nom policy for HW SDP throttling.
 - Add passthrough visual confirm.
 - Expand amdgpu_dm KUnit test coverage across cursor, MST, EDID, HDMI,
   IRQ, i2c, framebuffer, tiling/modifier and HPD paths.
 - Various fixes for Kunit tests related to HDMI FRL, IRQ and cursors.

Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:52 -04:00
Ivan Lipski
2cfa2341ce drm/amd/display: Guard amdgpu_dm_irq_schedule_work against NULL irq_wq
[Why&How]
An interrupt racing DM teardown can reach amdgpu_dm_irq_schedule_work()
after the IRQ workqueue is destroyed, passing a NULL wq to queue_work()
and crashing in __queue_work(). Bail out early when adev->dm.irq_wq is
NULL so a registered handler is simply not queued.

Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:50 -04:00
Nicholas Kazlauskas
dd67db7d28 drm/amd/display: Adjust vblank_nom policy for HW SDP tranmission reqs
[Why]
The requirement is that VSTARTUP has to come before vsync, line 0.
This means that the VSTARTUP has to be in the blank front porch.

The current implementation in DML2.1 does meet this requirement by
adjusting vblank_nom to the full vblank_avail but this has two
undesirable side effects:

1. When vblank is nominal this pushes VUPDATE on the line after VBLANK
   start. For Replay this gives only 1 line worth of time to program the
   SDP and blank the DPG. If we miss this window then we have to wait
   an entire frame before we can retry IPX entry. Residency is impacted.

2. The prefetch schedule is suboptimal. Instead of leveraging a very
   long vblank for power we wake early and block c-state earlier.

[How]
Use the same policy as prior ASIC - clamp the vblank_nom adjustment to
be the maximum of vblank_nom or the size of the back porch + 2 lines.
The back porch includes the vsync width in it in the calculation.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:48 -04:00
Dillon Varone
413e05b9ce drm/amd/display: Populate vblank_nom according to bounding box
[Why&How]
Wrapper currently populates the vblank nom as the entire blank for a
given timing. This should be constrained to a sane maximum but still
controlled by the caller's (wrapper) policy, which for now will be the
existing bounding box value.

Reviewed-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:46 -04:00
Gaghik Khachatrian
82e33a84ef drm/amd/display: Add passthrough visual confirm
- Added a new visual_confirm mode VISUAL_CONFIRM_DM_PASSTHROUGH so the confirm
  color is supplied by the DM instead of computed by DC.
- Relocated struct tg_color above dc_flip_addrs so it can be embedded by value.

Reviewed-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:44 -04:00
Bhawanpreet Lakha
8dade94422 drm/amd/display: Cover amdgpu_dm_create_i2c
Add KUnit tests for amdgpu_dm_create_i2c() covering the OEM i2c adapter
and the hardware i2c bus creation paths.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:41 -04:00
Bhawanpreet Lakha
fdd42268bc drm/amd/display: Cover amdgpu_dm_i2c_xfer
Add KUnit tests for amdgpu_dm_i2c_xfer() covering a failed hardware
command submission and the OEM i2c path with no device present.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:38 -04:00
Bhawanpreet Lakha
4827661d37 drm/amd/display: Cover hdmi_frl_status_polling_work
Add KUnit tests for hdmi_frl_status_polling_work() covering the
no-links, no-local-sink, non-HDMI and zero-FRL-rate skip cases, plus
the poll paths that leave the link unchanged or trigger a retrain.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:36 -04:00
Ivan Lipski
11b7722b8a drm/amd/display: Refactor hdmi_frl_status_polling_work for Kunit testing
[Why&How]
The KUnit connector test references hdmi_frl_status_polling_work(), but the
function was static with no visible prototype, causing a build failure
(undeclared / implicit declaration). Make the function non-static and add
a prototype to amdgpu_dm_connector.h so the test can reference it. The
INIT_DELAYED_WORK setup remains in amdgpu_dm_connector_init_helper(); no
runtime behavior change.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:40:30 -04:00
Bhawanpreet Lakha
d66d8a9717 drm/amd/display: Cover add_fs_modes illegal timing skip
Add a KUnit test for add_fs_modes() confirming that a generated mode
with illegal timing is skipped rather than added.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:19 -04:00
Bhawanpreet Lakha
78a72e3151 drm/amd/display: Cover add_fs_modes mode generation
Add KUnit tests for add_fs_modes() covering successful freesync-video
mode generation and refresh rates that fall outside the supported
range.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:16 -04:00
Bhawanpreet Lakha
5113a08a4b drm/amd/display: Cover amdgpu_dm_prune_primary_tile_modes
Add KUnit tests for amdgpu_dm_prune_primary_tile_modes() covering the
no-sink, no panel-patch and non-tiled early returns, a secondary tile,
and the primary-tile path that prunes per-tile modes.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:13 -04:00
Dillon Varone
875d9edba6 drm/amd/display: Fix mismatch number of OPP/DPP accounting
[WHY&HOW]
For cases where number of OPP/DPP mismatch, like 4 planes, 1 stream on
a 3 OPP ASIC, mode support would previously fail citing lack of OPP's.
This is incorrect, as the configuration only needs 1 OPP but 4 DPP's.

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:10 -04:00
Alex Hung
6b611a801f drm/amd/display: Test amdgpu_dm_dcn10_register_irq_handlers
[WHAT]
Add KUnit tests for amdgpu_dm_dcn10_register_irq_handlers() covering the
add_id() rejections for the VUPDATE and HPD sources and the
invalid-source guard in the VUPDATE_NO_LOCK loop, and for
amdgpu_dm_register_outbox_irq_handlers() rejecting a source with no
funcs table.

[HOW]
Reuse the shared registration fixture and the fake IRQ service that maps
no source IDs.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:08 -04:00
Alex Hung
276c9754b4 drm/amd/display: Test amdgpu_dm_dce110_register_irq_handlers
[WHAT]
Add KUnit tests for amdgpu_dm_dce110_register_irq_handlers() covering
the SOC15 DCE client used from Vega on, the amdgpu_irq_add_id()
rejections for the CRTC, VUPDATE and HPD sources, and the
invalid-source guards in the VBLANK, VUPDATE and PFLIP loops.

[HOW]
Add three fake IRQ services that map only a prefix of the source IDs so
each loop reaches its guard in turn. Clearing a single amdgpu_irq_src's
funcs makes only that source's add_id() fail.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:04 -04:00
Alex Hung
9a678a38d1 drm/amd/display: Test dm_dmub_outbox1_low_irq drain and work guards
[WHAT]
Add KUnit tests for dm_dmub_outbox1_low_irq() draining a trace ring up
to the DMUB_TRACE_MAX_READ cap, dm_handle_hpd_work() rejecting a work
item with no notification, and amdgpu_dm_irq_schedule_work() not
queueing once the IRQ workqueue is gone.

[HOW]
Back dmub->outbox0_rb with a fake ring whose write pointer sits one
entry past the cap, and keep the ring larger so the read pointer does
not wrap. dm_handle_hpd_work() returns before its own kfree() on the
NULL-notify path, so the test frees the work item.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:34:01 -04:00
Alex Hung
bd301aeed2 drm/amd/display: Test HPD RX, HPD init and DMUB callback branches
[WHAT]
Add KUnit tests for handle_hpd_rx_irq() re-detecting a downstream port
change on a non-MST-root connector, amdgpu_dm_hpd_init() skipping a
connector with no dc_link, and dmub_hpd_callback() deferring HPD while
suspended. Also add a writeback connector to the HPD registration test.

[HOW]
The downstream-change test reuses dm_test_setup_hpd_rx_irq() and clears
the MST root state, with dc_link_detect() stubbed to fail. The suspend
test leaves adev->dm.ddev NULL, so reaching the connector walk would
crash.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:59 -04:00
Alex Hung
3623121b15 drm/amd/display: Test handle_hpd_irq_helper detect and debounce exits
[WHAT]
Add KUnit tests for handle_hpd_irq_helper() covering a failing
dc_link_detect_connection_type() and the early return taken when a
debounce re-detect is already scheduled. Also arm the debounce work in
the stale-prev-sink test so mod_delayed_work() re-schedules.

[HOW]
Both build on dm_test_setup_hpd_irq_helper() and override only the
link_srv stubs they need. The pending-debounce test arms the work ten
seconds out and spies on dc_link_detect() to prove it was skipped.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:56 -04:00
Alex Hung
7c72657023 drm/amd/display: Test schedule_dc_vmin_vmax
[WHAT]
Add KUnit tests for schedule_dc_vmin_vmax(), which had no coverage. Both
callers are exercised: dm_crtc_high_irq() on an AI+ family and the DCE
path of dm_vupdate_high_irq() on a pre-DCE12 family.

[HOW]
Add a dm_test_setup_vmin_vmax_crtc() fixture building a CRTC with an
active VRR stream and a vmin/vmax work queue. Each test flushes the
queue and checks the worker applied the adjust and dropped its stream
reference.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:53 -04:00
Alex Hung
68f698eadd drm/amd/display: Test writeback handling in dm_crtc_high_irq
[WHAT]
Add KUnit tests for the two writeback vblanks in dm_crtc_high_irq(): the
first disables frame capture and marks wb_frame_done, the second signals
the out fence and clears the pending state.

[HOW]
dc_stream_fc_disable_writeback() dereferences dc->res_pool before its
NULL-stream check, so supply a dc with a fake IRQ service. The
completion test queues a bare drm_writeback_job and holds a vblank
reference for the completion's drm_crtc_vblank_put().

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:51 -04:00
Alex Hung
f2d90f2477 drm/amd/display: Test pageflip completion in the high IRQ handlers
[WHAT]
Add KUnit tests for pageflip completion: the non-VRR path in
dm_pflip_high_irq(), and the DCN VUPDATE_NO_LOCK paths in
dm_vupdate_high_irq() that deliver the event once the OTG reports no
flip pending, or retire the flip when there are no active planes.

[HOW]
Initialise DRM vblank and hold a reference to balance the handler's
drm_crtc_vblank_put(). A non-zero DCE IP version selects the DCN path,
and a NULL adev->dm.dc makes dc_get_flip_pending_on_otg() report no
pending flip.

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:47 -04:00
Alex Hung
694c52c80b drm/amd/display: Refactor amdgpu_dm_irq_test
[WHAT]
Several amdgpu_dm_irq tests were each open-coding the same setup. Share
it through three functions: dm_test_add_crtc(),
dm_test_setup_hpd_irq_helper() and dm_test_setup_irq_regs().

Assisted-by: Copilot:Claude-Opus-5
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:45 -04:00
Bhawanpreet Lakha
889f15060c drm/amd/display: Cover amdgpu_set_panel_orientation
Add KUnit tests for amdgpu_set_panel_orientation() covering the non-eDP
early return, the missing native mode case, and a panel that applies
the orientation quirk.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25 18:33:42 -04:00