* clk-aspeed:
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
clk: aspeed: Fix return value check in aspeed_cc_init()
clk: aspeed: Add reset controller
clk: aspeed: Register gated clocks
clk: aspeed: Add platform driver and register PLLs
clk: aspeed: Register core clocks
clk: Add clock driver for ASPEED BMC SoCs
dt-bindings: clock: Add ASPEED constants
* clk-lock-UP:
clk: fix reentrancy of clk_enable() on UP systems
* clk-mediatek:
clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built
clk: mediatek: Fix all warnings for missing struct clk_onecell_data
clk: mediatek: fixup test-building of MediaTek clock drivers
clk: mediatek: group drivers under indpendent menu
* clk-allwinner:
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: Support fixed post-dividers on MP style clocks
clk: sunxi: Use PTR_ERR_OR_ZERO()
* clk-remove-asm-clkdev:
clk: Move __clk_{get,put}() into private clk.h API
clk: sunxi: Use CLK_IS_CRITICAL flag for critical clks
arch: Remove clkdev.h asm-generic from Kbuild
clk: Prepare to remove asm-generic/clkdev.h
blackfin: Use generic clkdev.h header
* clk-debugfs-fixes:
clk: Simplify debugfs registration
clk: Fix debugfs_create_*() usage
clk: Show symbolic clock flags in debugfs
clk: Improve flags doc for of_clk_detect_critical()
* clk-renesas:
clk: renesas: r8a7796: Add FDP clock
clk: renesas: cpg-mssr: Keep wakeup sources active during system suspend
clk: renesas: mstp: Keep wakeup sources active during system suspend
clk: renesas: r8a77970: Add LVDS clock
* clk-meson:
clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()
clk: meson-axg: make local symbol axg_gp0_params_table static
clk: meson-axg: fix return value check in axg_clkc_probe()
clk: meson: mpll: use 64-bit maths in params_from_rate
clk: meson-axg: add clock controller drivers
clk: meson-axg: add clocks dt-bindings required header
dt-bindings: clock: add compatible variant for the Meson-AXG
clk: meson: make the spinlock naming more specific
clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks
clk: meson: gxbb: fix wrong clock for SARADC/SANA
* clk-iproc:
clk: iproc: Minor tidy up of iproc pll data structures
clk: iproc: Allow plls to do minor rate changes without reset
clk: iproc: Fix error in the pll post divider rate calculation
clk: iproc: Allow iproc pll to runtime calculate vco parameters
* clk-mvebu:
clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()
* clk-qcom-a53:
clk: qcom: Add APCS clock controller support
clk: qcom: Add regmap mux-div clocks support
clk: qcom: Add A53 PLL support
* clk-at91:
clk: at91: pmc: Support backup for programmable clocks
clk: at91: pmc: Save SCSR during suspend
clk: at91: pmc: Wait for clocks when resuming
* clk-imx7ulp:
clk: Don't touch hardware when reparenting during registration
* clk-axigen:
clk: axi-clkgen: Round closest in round_rate() and recalc_rate()
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()
* clk-si5351:
clk: si5351: _si5351_clkout_reset_pll() can be static
clk: si5351: Do not enable parent clocks on probe
clk: si5351: Rename internal plls to avoid name collisions
clk: si5351: Apply PLL soft reset before enabling the outputs
clk: si5351: Add DT property to enable PLL reset
clk: si5351: implement remove handler
* clk-pxa:
clk: pxa: unbreak lookup of CLK_POUT
* clk-qcom-alpha-pll:
clk: qcom: add read-only alpha pll post divider operations
clk: qcom: support for 2 bit PLL post divider
clk: qcom: support Brammo type Alpha PLL
clk: qcom: support Huayra type Alpha PLL
clk: qcom: support for dynamic updating the PLL
clk: qcom: support for alpha mode configuration
clk: qcom: flag for 64 bit CONFIG_CTL
clk: qcom: fix 16 bit alpha support calculation
clk: qcom: support for alpha pll properties
* clk-check-ops-ptr:
clk: check ops pointer on clock register
* clk-protect-rate:
clk: fix set_rate_range when current rate is out of range
clk: add clk_rate_exclusive api
clk: cosmetic changes to clk_summary debugfs entry
clk: add clock protection mechanism to clk core
clk: use round rate to bail out early in set_rate
clk: rework calls to round and determine rate callbacks
clk: add clk_core_set_phase_nolock function
clk: take the prepare lock out of clk_core_set_parent
clk: fix incorrect usage of ENOSYS
* clk-omap:
clk: ti: Drop legacy clk-3xxx-legacy code
The USB port 1 clock gate control has an inversed polarity
from all the other clock gates in the chip. This makes the
aspeed_clk_{enable,disable} functions honor the flag
CLK_GATE_SET_TO_DISABLE and set that flag appropriately
so it's set for all clocks except USB port 1.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In case of error, the function of_iomap() returns NULL pointer not
ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.
Fixes: a2e230c7b2ea ("clk: Add clock driver for ASPEED BMC SoCs")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There are some resets that are not associated with gates. These are
represented by a reset controller.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The majority of the clocks in the system are gates paired with a reset
controller that holds the IP in reset.
This borrows from clk_hw_register_gate, but registers two 'gates', one
to control the clock enable register and the other to control the reset
IP. This allows us to enforce the ordering:
1. Place IP in reset
2. Enable clock
3. Delay
4. Release reset
There are some gates that do not have an associated reset; these are
handled by using -1 as the index for the reset.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This registers a platform driver to set up all of the non-core clocks.
The clocks that have configurable rates are now registered.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This registers the core clocks; those which are required to calculate
the rate of the timer peripheral so the system can load a clocksource
driver.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This adds the stub of a driver for the ASPEED SoCs. The clocks are
defined and the static registration is set up.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The hardware description for the DE2 clocks on the A64 and H5 SoCs is
fixed, and support for these clocks on the H3 is added. Also, the
description for the TCON1 clock on the A83T is fixed. All these are
non-critical, as they have no users.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAlpS6O4OHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDB+exAAnM/bWFyjJTdSEkKu3y1R9O1kCJ9IccCg8Y+k
WN0/rl3Afh40lr6hwa3rS4DqROtjyMSU421nJIlnU6MyBLkNokCJvnibKbltoFNY
QXg96QfSoD0ThdEOkro4nt0y4FdLZ31YQ3DFqhs6X0uxgMOUQUrcs+0a1m28zVj6
zCXcf4GT3DodrhyF5StqBnR3znNY/NxlBYomPfv8MSD5mG1Zqi1So1FwTaqiyF5d
oIxwSg+tBltrXloV1fJmgWFkM18WRQvoAEkEWRxwILKrmzLr2m/XI91M+xcRkjym
X++CLIEhK2dsVu2jOLwFv6/51fkaWI8FjU+0ZNrZR/rdpBMvCCPgyjcqnxtMiTv/
F4j5NWME5C3vtsAjHxdJEK10zC/CmG+0G7exP4k6Gf/Ril4otE5nJBfnrXwmAPvy
3hv8R7eTngaxU/RQhiH920W1hfCDfaEILsDEXiWTgiLfN7jHv41Z9K9Di/9UCuUc
rZ5fsAvRr/+AKnx/fXIWEz4LrieXIgPHYcq9Gd8I8S718tog9nPSXot7sMYQSGVy
RXAW7CuMSm82glnTlwrH8cV/MmBoAHUuOsTktacfPHxNruyz5JOo1JNb95lj7B1F
A9Uk6dYs2MYxNI4wSWjRB7G/hQMXaTYLd+wvLbqtObkg+d+/w0vM0Vx6vFGumTHv
YMVu+4w=
=bN56
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clock changes from Chen-Yu Tsai:
- Fix hardware description for the DE2 clocks on the A64 and H5 SoCs
- Support DE2 clocks on the H3
- Fix description for the TCON1 clock on A83T
All these are non-critical, as they have no users.
* tag 'sunxi-clk-for-4.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
Changes from v1->v2:
Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable
reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should
be quite reasonable because the reset controller is tightly embedded
inside and exported from these clock subsystems. At least it can be found
on infracfg and pericfg subsystem that both are really fundamental block
lots of devices must depend on.
commit 74cb0d6dde ("clk: mediatek: fixup test-building of MediaTek clock
drivers") can let the build system looking into the directory where the
clock drivers resides and then allow test-building the drivers.
But the change also gives rise to certain incorrect behavior which is
reset.c being built even not depending on either COMPILE_TEST or
ARCH_MEDIATEK alternative dependency. To get rid of reset.c being built
unexpectedly on the other platforms, it would be a good change that the
file should be built depending on its own specific configuration rather
than just on generic RESET_CONTROLLER one.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reentrant calls to clk_enable() are not working on UP systems. This is
caused by the fact spin_trylock_irqsave() always returns true when
CONFIG_SMP=n (and CONFIG_DEBUG_SPINLOCK=n) which causes the reference
counting to not work correctly when clk_enable_lock() is called twice
before clk_enable_unlock() is called (this happens when clk_enable()
is called from within another clk_enable()).
This fixes the problem by skipping the call to spin_trylock_irqsave() on UP
systems and relying solely on reference counting. We also make sure to set
flags in this case so that we are not returning an uninitialized value.
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
platform_get_resource() may return NULL, add proper
check to avoid potential NULL dereferencing.
This is detected by Coccinelle semantic patch.
@@
expression pdev, res, n, t, e, e1, e2;
@@
res = platform_get_resource(pdev, t, n);
+ if (!res)
+ return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- Add support for the FDP1-0 module clock on R-Car M3-W.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJaT1BcAAoJEEgEtLw/Ve77YtoQAKBi3VfnAGXIudXWue31G2ml
zP6mCm5907MoXYcs8PrG9036TPkXvdbBLZIfA6XDfwNPMJbPU/soZrWM3+o/QG1V
AzR1ea7G/h6wL6ArSI4K+uouqVtNPo7ugjGt+JMvB4t0JXdduvrJZ6dyc2hj98O8
rbPdyAgFkwfZzPn6LNWlDp9075oxVg7c6xFfBEAvVY+brrMYb2VRtllmQcNEHs+X
SYHF9eccafABuCmmFMpHX3BTy/trhqpWN5G+vc07XAfUIN9Nk3ubdtWqsIzebmAN
QH7XNq1hJ9GjfGXP+Dt12GLvuAAi5jTtpXP2BNwfzQUGniUQXPQLdWIyxV6l7pZC
7EMDJ0J2Y9q3SjeheMGCucwTQMJs61lQdrQEBImSRx3ZyXTyZVEjz5qm1cRa+wFG
pTIGAWjXJv3aZpTZnyuqtyhMkvpLf5DQe0pgI0zZITlcFwAFuK99h2sbYWzDIbgL
9CNfe+6euPXQgTgGdaTKx/tu7IuAcbWW9sKxEHThG6V3X1T0+dMGAtQo6Dfi6vaJ
Pfhd3vqUGgTZIIOeRweukRO4fICj0UK2lHvyX4P/4LcY+2gvDGvpKPO3dcSEouKF
RxxxsQHOuaJp6z2kMfKPfQTaCKGm0Y250w1i0ZhCCZQl8C9GB7d4iTtKE62nSu59
pAab+SwANTuTScVCPZ6h
=ITM6
-----END PGP SIGNATURE-----
Merge tag 'clk-renesas-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver update from Geert Uytterhoeven:
- Add support for the FDP1-0 module clock on R-Car M3-W
* tag 'clk-renesas-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a7796: Add FDP clock
When exposing data access through debugfs, the correct
debugfs_create_*() functions must be used, matching the data
types.
Remove all casts from data pointers passed to debugfs_create_*()
functions, as such casts prevent the compiler from flagging bugs.
clk_core.rate and .accuracy are "unsigned long", hence casting
their addresses to "u32 *" exposed the wrong halves on big-endian
64-bit systems. Fix this by using debugfs_create_ulong() instead.
Octal permissions are preferred, as they are easier to read than
symbolic permissions. Hence replace "S_IRUGO" by "0444"
throughout.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[sboyd@codeaurora.org: Squash the octal change in too]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently the virtual "clk_flags" file in debugfs shows the numeric
value of the top-level framework flags for the specified clock.
Hence the user must manually interpret these values.
Moreover, on big-endian 64-bit systems, the wrong half of the value is
shown, due to the cast from "unsigned long *" to "u32 *".
Fix both issues by showing the symbolic flag names instead.
Any non-standard flags are shown as a hex number.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
We can move these APIs into the private header file now that we
don't have any users of the __clk_get() and __clk_put() APIs
outside of clkdev.c and clk.c.
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
We'd like to privatize __clk_get(), but the sunxi clk driver is
calling this function to keep a reference held on the clk and
call clk_prepare_enable() on it. We support this design in the
clk core now with the CLK_IS_CRITICAL flag, so let's just use
that instead.
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The "flags" parameter passed to of_clk_detect_critical() cannot be a
pointer to a real clk_core.flags field, as clk_core is private to the
clock framework internals.
Change the comment to refer to top-level framework flags instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that every architecture is using the generic clkdev.h file
and we no longer include asm/clkdev.h anywhere in the tree, we
can remove it.
Cc: Russell King <linux@armlinux.org.uk>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: <linux-arch@vger.kernel.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
TCON1 also has M divider, contrary to TCON0. And the mux is only
2 bits wide, instead of 3.
Fixes: 05359be117 ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[wens@csie.org: Add description about mux width difference]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This tag is required for the ARM SoC and clk trees in the 4.16 merge
window. It contains the clock binding header that is used by the ASPEED
clk driver and the device trees.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJaPG/NAAoJEGt2WQeBR3Ce37wP/3exHj4+EwsopXd0s+c3kxYg
YZFlKkCPfBM36CW+jyfIqXIMumfP1Ad0StGoKKruq2an40AdIwblKpjecRnEY3Lq
saFG/qSBunaW/vd+mTzlMxbQ6s0/37IZljTlyqFaA3yKOS5tbeNbCJDH/ptmAdY5
qvfhPjTq3VbOGvL7sShCuiS+yUmQy4klcpj2bLs7Um3ao0/5MgA7ZkzhBwDjR30K
lkk7RAhKJ4EZrou9QY5ExHky3T19OPqXHBKdf6BU/6PP3nA/Rp5BDOwu5NiWx+B3
0qoURJJdKEYe29gO/mjkcFjxS46JH9m27fajZ9DyJkh8fZ9h2yhMRSbIK7W+p0ul
XyRwMOZFkf3J19mUFvTNclIpWl8Sx8ygogQhpeApe1sSw+wQKFiygdeGF67kImHR
ilVOgAxRnRSXR0Hguqq25MGQhE3QhACspENrxkvqLz1NbhR3+3NVo/7M7Gti6J6b
4Mww6dmqqcXd3GFh7cbWg705OIuidxVsjw3G/ythcT037gHVIQS/nJQzIucsRKeA
wuJ72q67Ip9+4SixGLkucU+3xkYwqua4bnOJTpWNFrHhsNWwwBstMphUeLzjt2i5
TVOsIumJMT6V9HtadnhCRnfFcR20YjVJnbzpORzRk5qrUAdNfmZ8fx1uZCQuGL7d
YUoTlw06LEtRx5Lyfz9i
=z4vq
-----END PGP SIGNATURE-----
Merge tag 'aspeed-4.16-clk-binding' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into HEAD
dt-bindings: Clock binding for ASPEED SoCs
This tag is required for the ARM SoC and clk trees in the 4.16 merge
window. It contains the clock binding header that is used by the ASPEED
clk driver and the device trees.
* tag 'aspeed-4.16-clk-binding' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
dt-bindings: clock: Add ASPEED constants
Now that all the users of asm/clkdev.h have been replaced with
the generic file we can get rid of the asm-generic file as well
and implement that code directly where it's used.
We only have one caller of __clkdev_alloc(), in clkdev.c so we
can easily remove that and drop the include of asm/clkdev.h in
linux/clkdev.h by putting the __clk_get/__clk_put inlines in
their respective location.
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a driver for the APCS clock controller. It is part of the APCS
hardware block, which among other things implements also a combined
mux and half integer divider functionality. It can choose between a
fixed-rate clock or the dedicated APCS (A53) PLL. The source and the
divider can be set both at the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Include rcg header for parent_map, drop
multiple unneeded includes, add COMPILE_TEST to APCS depends,
made tristate/modular]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Change a comment style, drop parent_map in
favor of a u32 array instead, export symbols for clk_ops and mux
function]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.
This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Move to devm provider registration,
NUL terminate frequency table, made tristate/modular]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3
DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE
module clock).
Fix this by change the clock descriptions to use the clocks of H3.
Fixes: 763c5bd045 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.
Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a6 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
divider_recalc_rate() is an helper function used by clock divider of
different types, so the structure containing the 'hw' pointer is not
always a 'struct clk_divider'
At the following line:
> div = _get_div(table, val, flags, divider->width);
in several cases, the value of 'divider->width' is garbage as the actual
structure behind this memory is not a 'struct clk_divider'
Fortunately, this width value is used by _get_val() only when
CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so
far when the structure is not a 'struct clk_divider'. This is probably
why we did not notice this bug before
Fixes: afe76c8fd0 ("clk: allow a clk divider with max divisor when zero")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fix ptr_ret.cocci warnings:
drivers/clk/mvebu/armada-37xx-periph.c:362:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There were a few fields in the iproc pll data structures that were
holding information that was not true state information.
Using stack variables is sufficient and simplifies the structure.
There are not any functional changes in this commit.
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The iproc plls are capable of doing small rate changes without the
need for a full reset and re-lock procedure. This feature will
allow for small tweaks to the PLL rate to occur smoothly.
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The pll post divider code was using DIV_ROUND_UP when determining the
divider value best suited to produce the target frequency.
Using DIV_ROUND_CLOSEST will give us better divider values when
the division results in a small remainder.
Also, change the post divider clock over to the determine_rate api
instead of round_rate.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the ability for the iproc pll to calculate the pll parameters at
runtime instead of only using predefined tables. This ability allows
the clock users to select from the full range of vco frequencies.
The old method of table based programming is retained so that existing
users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM
will need to be set to enable the new runtime calculation method.
Currently, this is only being enabled for the audio pll.
This feature also revealed a problem with the driver using the
round_rate api. The round_rate api does not allow for frequencies larger
than 2^31 to be returned. Those large frequencies are interpreted as an
error code. Therefore, we are moving to the determine_rate api which
solves this problem.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fixed-post-divider support is added for two types of our clocks.
This in turn is used to support odd clocks on some of our SoCs.
On the A64, the MMC module clocks have a hidden post-divider.
On the A83T, a post-divider is needed to support programming
sigma-delta modulation with known fixed parameters from the
BSP kernel for the audio PLL.
There's also a small cleanup to use the shorter PTR_ERR_OR_ZERO
macro in various functions.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAlpEkeEOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDBpwhAAlWd2kbzI/lLevi69wXOsVH2keWfnD8Pr8DxJ
4aONajdldN9RfCCaeJtYhqCDW5rEvAJH88msVH0IYwy8NbeWSPAxDyQX5WW3Ugj8
UUmm+fWcoTY9ePJ3lFDgx2LzI7zyolzsSuqk93lVZi8fi1xUYQ4e/Z7fHj9ONNXD
1xjPmHU1SXwtrufJ2qIE35K2zCmCnlgIITO8uGPwppg03sLfkSnOLvrCzYhlKv1r
xqfncyLQdg/XOONV9QYDtn3b2M9A+CYqV6eojqbZFFFbOkqqaSyfGJ8T7o/nEd4n
k+QmDwg5AqQadWPPScddw+AIeyDD2FhMFhWu7+3A09iMHom+BrMm5QRChRBDwnmI
sFoLoMmfjCjVvrvZI/R4tGfKyAJFyQ6fEwz6yuCNt8DWwfkE1yrOmK8uZUiQMZeq
0R1AOVbTzM5a0X35OWJK5wV5Pa1rwu4bSup9QVYYzIjYW4ZWVVaQBYONmuUlVPhI
lavgvD+C5BoiW2QFr54yJrDwTPifuh9k5I6rKMCUSbktmgE/3xuRX04RuGvyFO30
vJP2QxA2D+0I6ItqAAz7CaGzb2QOB4eBk0ayXNT5Sjcp8dU1pClVZtPVUCpgpJ/F
2/CzPqr1qnUPJJ+W6hy1AXl6mVah5eAIlmRDAwVDrHlYrNVNtU1AbxQrZaymAu87
3ntffVk=
=IevL
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clock changes from Chen-Yu Tsai:
"Fixed-post-divider support is added for two types of our clocks.
This in turn is used to support odd clocks on some of our SoCs.
On the A64, the MMC module clocks have a hidden post-divider.
On the A83T, a post-divider is needed to support programming
sigma-delta modulation with known fixed parameters from the
BSP kernel for the audio PLL.
There's also a small cleanup to use the shorter PTR_ERR_OR_ZERO
macro in various functions."
* tag 'sunxi-clk-for-4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: Support fixed post-dividers on MP style clocks
clk: sunxi: Use PTR_ERR_OR_ZERO()
Since switching to clk drivers, the CLK_POUT cannot be searched for by
clk_get() API and thus it returns with ENOENT.
Register it with the clk_lookup and thus unbreak the users of it.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fixes the following sparse warning:
drivers/clk/meson/axg.c:260:25: warning:
symbol 'axg_gp0_params_table' was not declared. Should it be static?
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In case of error, the function devm_ioremap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.
Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Even though the header file linux/clk-provider.h is already being properly
included in clk-mtk.h, the definition of struct clk_onecell_data still
must depend on CONFIG_COMMON_CLK defined and thus it's possible that
below build warnings occur when CONFIG_COMMON_CLK is not being selected.
Therefore, these functions which need struct clk_onecell_data without
declaring that structure first requires simply declaring that this struct
exists prior to referencing it in clk-mtk.h
Changes from v1->v2:
enhance v1 based on two useful solutions Jean Delvare kindly suggested.
All warnings (new ones prefixed by >>):
In file included from drivers/clk/mediatek/reset.c:22:0:
>>drivers/clk/mediatek/clk-mtk.h:44:19: warning: 'struct clk_onecell_data'
declared inside parameter list will not be visible outside of
this definition or declaration
int num, struct clk_onecell_data *clk_data);
^~~~~~~~~~~~~~~~
drivers/clk/mediatek/clk-mtk.h:63:19: warning: 'struct clk_onecell_data'
declared inside parameter list will not be visible outside of
this definition or declaration
int num, struct clk_onecell_data *clk_data);
^~~~~~~~~~~~~~~~
drivers/clk/mediatek/clk-mtk.h:145:10: warning: 'struct clk_onecell_data'
declared inside parameter list will not be visible outside of
this definition or declaration
struct clk_onecell_data *clk_data);
^~~~~~~~~~~~~~~~
drivers/clk/mediatek/clk-mtk.h:164:11: warning: 'struct clk_onecell_data'
declared inside parameter list will not be visible outside of
this definition or declaration
struct clk_onecell_data *clk_data);
^~~~~~~~~~~~~~~~
drivers/clk/mediatek/clk-mtk.h:190:12: warning: 'struct clk_onecell_data'
declared inside parameter list will not be visible outside of this
definition or declaration
struct clk_onecell_data *clk_data);
^~~~~~~~~~~~~~~~
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: kbuild-all@01.org
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Jean Delvare <jdelvare@suse.de>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
