Add a small section dispatch table and record AMD crashdump sections as
RAS_LOG_EVENT_BOOT events. Preserve the original section GUID,
severity, and a bounded copy of the section payload so the existing boot
CPER generator can emit records for debugfs consumers.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add local HEST status and data entry layouts. Also add local helpers for
revision-aware payload access, entry walking, and basic status
validation.
Move the BERT record processing prototype into a dedicated BERT header
so the parser interface stays local to the BERT parser code.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ras_core_get_ras_block_name() indexes ras_block_name[] directly
with enum ras_block_id values. The table only covered entries through
RAS_BLOCK_ID__MPIO, while ras.h defines additional blocks through
RAS_BLOCK_ID__UCIE_PCS.
When UniRAS reports a newer block such as RAS_BLOCK_ID__PCIE_PL,
the lookup falls past the end of the table and returns an empty string.
That leaves messages such as "new correctable hardware errors detected
in block" without the block name.
Fill in the missing names in enum order so the indexed lookup can
resolve PCIE_PL and the other existing ras_block_id values.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a parameter to differentiate callers that need new error
count vs total count, ensuring the new count is only cleared
by the intended caller.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use a common interface to retrieve poison support status
to avoid handling ASIC-specific logic.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The eeprom ras table can be quite large, and each read requires multiple
smu i2c transactions (max 24 bytes per transfer). Limit the validation
to avoid excessive i2c traffic and CPU busy-wait overhead.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use flip-bit mask to generalize bad page address derivation in a row.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add management interface to support psp bad page address translation.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Read and cache the ACPI BERT payload during MCE hardware init, then ask
rascore to process the cached records once for each GPU socket.
Reset the cached state when the MCE notifier chain is torn down so a new
initialization sequence can poll and process boot errors again.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a rascore BERT record walker that validates cached BERT generic
status blocks and iterates their CPER section descriptors.
The generic APEI BERT path may have already consumed the boot error
region and cleared block_status before AMDGPU caches the payload, so do
not use block_status to decide whether cached records should be parsed.
Section-specific parsers can be added separately on top of this walker.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Map boot RAS log events to the boot CPER type so records from
boot-time error sources use the intended CPER record classification.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add the PCIE_PL ACA HWIP mapping for ACA v5 hardware so MCE banks
with HWID 0x1e1 and ACA type 0x0 can be decoded by the RAS ACA path.
Register PCIE_PL as a RAS block using the default ACA bank match and
parse helpers, matching the other simple v5 block mappings.
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Update aca bank decoding for A + A.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The socket ID parsed from ACA IPID always corresponds to the current
socket and never references another socket. Therefore, there is no
need to maintain per-socket storage for remote sockets — a single
socket is sufficient to store all ACA RAS error information for each
GPU device.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- Adding a new interface in guest driver to parse the pf2vf message and
return RAS capability to the caller when uniras is enabled
- Update RAS capability fields in amdgv_sriovmsg.h for uniras
Signed-off-by: Jiahao Li <Jiahao.Li@amd.com>
Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
support multi-parameter communication with mp1 in ras_mp1_v15_0.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
update mp1_v13_0 to use smu ras multi-parameter interface.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Update the dedicated smu ras message interface to accept multiple
parameters on each call.
v2:
Add input parameter validation.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Share memory region between VF RAS_CMD buffer and legacy RAS telemetry as
they are mutually exclusive based on UniRAS state
Signed-off-by: Jiahao Li <Jiahao.Li@amd.com>
Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Introduce a toggle to control whether RAS RL and TA firmware are loaded
through the legacy path or the RAS module.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Allow the RAS module to load RAS RL and TA firmware internally while
maintaining backward compatibility with the system-level firmware
loading path.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Optimize the memory usage to accommodate both referencing externally
allocated memory from outside the module and allocating memory directly
within the module.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When uniras owns the RAS TA, rascore can no longer rely on the legacy
PSP context to keep TA session state alive across reset or suspend.
The manager has to provide enough metadata to reload the TA and rebuild
its shared buffer after PSP reinitialization.
Source TA firmware metadata from adev->psp.ras_context.context.bin_desc,
allocate and free the shared buffer on demand, and hand the fini
cleanup back to rascore through a put_ras_ta_fini_param callback. Add a
resume hook that reloads the TA with skip_lock set so the reload can
run after GPU reset.
Export thin ras_mgr helpers for feature toggles and deferred replay so
higher layers can use the rascore-owned TA path without depending on
legacy PSP-managed TA session state directly.
Signed-off-by: Jinzhou Su <jinzhou.su@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stop deriving RAS TA session state from the legacy PSP status query and
switch ras_psp over to locally tracked TA lifetime. Delegate TA init
parameters and fini cleanup through ras_psp sys callbacks, update the
load and unload flow to keep firmware metadata in rascore, and add a
skip_lock load path that can be used after PSP reinitialization.
This prepares ras_psp for a later ras_mgr resume hook that reloads the
TA without relying on legacy PSP-managed session ownership.
Signed-off-by: Jinzhou Su <jinzhou.su@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
On A+A, when ras_enabled is 0, the RAS debugfs node is
not deleted when the driver is uninstalled.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add bad page preloading and pre-reservation support.
v2:
Add modification to ensure amdgpu_sw_init does not fail
and remove deferred ras instance release.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- Since EEPROM threshold configuration is record count, use
record count instead of bad page count for EEPROM threshold
checking.
- RMA check and notification have been moved to ras_eeprom_mgr.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Support obtaining bad page info at boot time for ras_mp1_v15_0.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Preload bad pages occur during the sw_init stage, so
the preload-related code in RAS module must be moved
to sw_init for proper initialization.
v2:
Rename functions and variables.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rework fw eeprom handling for new management interface:
- Support new eeprom management interfaces.
- Use ras_mp1 common interfaces to retrieve bad page information
- Keep a local backup to reduce the interaction frequency with MP1.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Switch to use new eeprom management interfaces.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- Refactor EEPROM parameter config to support multiple ras EEPROMs.
- Convert bad page count to record count as EEPROM threshold.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Support retrieving bad page info from mp1_v15_0.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ras mp1 introduces common interfaces to manage mp1 data
obtained from different ASICs.
v2:
Add mutex to ensure complete data transactions with MP1.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
