[why]
Block level sequence operations should not use global state structs such
as pipe_ctx. OPTC_PIPE_CONTROL_LOCK is a BLS with complex logic
dispatching a lot of smaller hardware programming operations.
BLS should be a simple and atomic hardware operation without performing
mutations or having an access to global state. All operations on global
state should be moved to build step in HWSS.
[how]
- Split OPTC_PIPE_CONTROL_LOCK into substeps:
- HUBP_WAIT_FLIP_PENDING,
- TG_SET_GSL,
- TG_SET_GSL_SOURCE_SELECT,
- TG_LOCK,
- TG_3DLUT_WA_UNLOCK.
- Add hwss_pipe_control_lock - for in place build + execution.
- Remove timeout from HUBP_WAIT_FOR_FLIP_PENDING.
- Move software logic to builder. which fills pipe_control_lock_params
containing data for programming actual hwss blocks.
- Due to differences in what pipe control lock means bettween
asics following builder variants are added:
- dce_build_pipe_control_lock_sequence for asics pre DCN20,
- dcn20_build_pipe_control_lock_sequence.
- Rework gsl group programming to use builder / executor pattern.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Pipe_ctx shouldn't be passed as block sequence block parameter.
[How]
- Adjust arguments for:
- set_input_transfer_func,
- populate_mcm_luts,
- set_mcm_location_post_blend,
- set_mcm_luts,
- program_rmcm_luts.
- Remove const qualifier from plane_state in set_mcm_luts since it is
mutated.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Tomasz Siemek <Tomasz.Siemek@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
Updates and fixes to HPO functionality, initialization, encoder
configuration and platform-specific behavior.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
amdgpu_dm_crtc_get_cursor_mode() returns DM_CURSOR_NATIVE_MODE early and
unconditionally for dcn4.x. That early return was added because these
ASICs no longer have the cursor-on-scaled-plane or cursor-on-yuv-plane
restrictions of older DCN, so native cursor is fine in those cases.
However, it also bypasses the "does the top plane fill the CRTC?" (hole)
evaluation further down. When the top/primary plane does not cover the
whole CRTC, the cursor must fall back to an overlay plane so it is
composited over the uncovered region; keeping the native cursor there
produces an incorrect result. As a consequence
igt@amdgpu/amd_cursor_overlay@non-full, which verifies exactly this
native->overlay fallback, fails on dcn42.
[how]
Change unconditional early return with a skip_fmt_scale_restrictions flag.
For dcn4.x keep skipping the YUV / active-color-pipeline / different-scale
overlay triggers (genuinely unnecessary on this hardware), but fall
through to the existing entire_crtc_covered check so a top plane that does
not fill the CRTC still selects DM_CURSOR_OVERLAY_MODE. Native mode is
still chosen when the plane covers the whole CRTC.
Update the amdgpu_dm_cursor KUnit tests accordingly: exercise the dcn4x
path with a full atomic state fixture (full coverage -> native) and add a
dcn4x hole case (top plane does not fill the CRTC -> overlay).
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: James Lin <PingLei.Lin@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reporting the RAS capability mask through the ras "features" sysfs node
changed the layout that node has always used, so the existing consumer
misreads it on the parts it already supports. XGMI error injection then
targets the wrong device and the RAS TA rejects it with
RAS_TA_STATUS__ERROR_PCS_STATE_HANG.
Keep the established layout on parts released before the new one, and
stop assigning the multi bit adev->ras_enabled to the single bit en
field.
Fixes: 375f15db1e ("drm/amdgpu: Support obtaining ras capabilities")
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The default bad page threshold is derived from the VRAM reserved for
retirement, but ras_eeprom_i2c_config() hardcodes
RAS_RESERVED_VRAM_SIZE_DEFAULT. amdgpu_ras_validate_threshold() instead
derives it from con->reserved_pages_in_bytes, which
amdgpu_ras_init_reserved_vram_size() doubles on MP0 v13.0.14.
That part therefore ends up with a 128 bad page threshold where it
should have 256, and reaches the limit after half as many retirements
as intended.
Reuse the value already computed for con->reserved_pages_in_bytes
rather than deriving it again, so the two cannot drift apart.
Fixes: c32092c39f ("drm/amd/ras: Refactor EEPROM parameter config to support multiple ras EEPROMs")
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
psp_ras_enable_features() returns 0 without sending anything once the
RAS TA is loaded by ras_mgr, and nothing on that path sends
ENABLE_FEATURES either. GFX RAS features therefore end up enabled by no
one, silently, because the helper still reports success.
This is harmless at boot, where the TA is loaded with poison_mode_en set
while GFX is freshly initialized. It is not harmless across a reset: a
mode2 reset clears the GFX side, amdgpu_gfx_ras_late_init() re-runs from
the reset handler but its enable request goes nowhere, and GFX stops
raising SQ EDC_FED. The visible effect is that only the first poison
injection after boot is ever consumed. Every later one creates the
poison in HBM and is never reported, since the first injection triggers
the reset that breaks reporting.
Add ras_psp_enable_features() to send ENABLE_FEATURES/DISABLE_FEATURES
to the TA owned by ras_mgr, and route amdgpu_ras_feature_enable()
through it. Newer parts arm RAS features inside the TA and must not be
toggled by the driver, so restrict the request to GFX IP versions below
12.1.0.
Fixes: e21b4356a3 ("drm/amdgpu: add switch to select firmware loading path for RAS RL and TA")
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The CPER command reports the next batch ID as the latest valid record
and does not handle a request starting at the write pointer. Batch trace
responses also copy only the ACA interpretation of the log union.
Report the latest valid CPER ID, select the preceding record for a write
pointer request, expose a bounded command transfer size, and copy the
complete log body for batch trace records.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
IA processor and Platform Memory BERT sections are system-wide records
and must not be copied into every GPU RAS ring. Per-socket GPU records
still need to be offered to each matching GPU.
Assign platform sections to the first eligible RAS instance and claim
each GPU socket before parsing its cached BERT data. Serialize ownership
with the shared mutex and retain the state until the final RAS device
exits.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
BERT may contain structured AMD crashdump, IA processor, Platform
Memory, PCIe, and SMN sections. Replaying all sections for every GPU
either duplicates GPU records or drops CPU and platform records when
their topology IDs are compared with GPU OAM IDs.
Parse the supported section formats in rascore. Route GPU records using
the OAM identity and gate CPU and platform sections through an explicit
owner selected by the operating-system integration layer.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Processor CPER generation needs the APIC ID and bank number from the
x86 machine-check record. CPU banks must also be logged by only one GPU
to avoid duplicate processor records.
Copy the APIC ID and bank number into the rascore ACA bank and route CPU
banks through the first registered GPU. Keep GPU banks routed by their
decoded socket ID.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Preserve standard Platform Memory sections recovered from BERT instead
of wrapping them in the AMD crashdump format.
Validate each boot section, copy its raw payload unchanged, align each
complete record to a 32-bit boundary, and report the exact serialized
size.
Route Platform Memory records through a dedicated generator,
independently of crashdump and processor records.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Encode runtime CPU machine checks with the standard IA Processor
section, including APIC ID, machine-check status, bank MSR address, and
SMCA register context.
Also preserve IA Processor sections recovered from BERT as
boot-notified records with their original context metadata and variable
payload size.
Route both forms through a processor-specific generator so they remain
separate from AMD crashdump records.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Populate the AMD crashdump common header and error information before
serializing fatal and boot records.
Validate that batched boot records share a section type, clamp the
register context to the crashdump payload, and account for each record
header when sizing the output.
Keep AMD record dispatch in a dedicated helper so processor and
Platform Memory generation can be added independently.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CPU machine-check and platform boot errors require standard processor
and Platform Memory section definitions. The AMD crashdump format also
uses a 64-byte common header followed by a common error information
structure.
Add the required GUIDs, validity fields, processor structures, and AMD
crashdump wire layout so rascore can generate each record type.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Processor CPER generation needs the APIC ID and machine-check bank
number in addition to the ACA register values. Logging the full internal
ACA bank also exceeds the stable fixed-size log body representation.
Carry the APIC ID and bank number with incoming ACA banks and store CPU
MCE events in a compact 128-byte log context for later CPER encoding.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Machine-check records may not carry the hardware-maintained UMC error
count expected by the normal polling path. As a result, valid deferred,
uncorrected, and corrected MCE status values can remain unclassified.
For MCE-originated banks, classify the error directly from the MCA
status bits when normal UMC decoding does not produce an error count.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
GPU MCE handling queues bank data directly in the MCE FIFO and only
needs to wake the RAS processing thread. Requiring a separate event
request prevents this path from scheduling processing when no event
object is available.
Permit a NULL request to skip event queue insertion while still
incrementing the interrupt request count and waking the processing
thread.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Keep BERT boot-error handling owned by the BERT module instead of letting
the MCE notifier lifecycle drive BERT processing and cleanup.
Group the cached boot-error state into a single structure so the related
poll result, raw record data, per-socket write tracking, and lock are
managed together.
Expose only the standard BERT sw_init/sw_fini entry points. The RAS manager
calls them around the existing MCE sw lifecycle, while the MCE code no
longer includes BERT headers or calls BERT helpers directly.
This lets BERT process cached boot records earlier in the RAS manager
sw_init path and release its cached state independently during sw_fini.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fix an issue where the saved bad page count is always zero.
The cur_nps_valid_page_num field in the record already tracks
the available bad page count, so use it directly to calculate
the correct saved bad page number.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Filter out invalid pages from extended page addresses.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Restructure ras cper to improve extensibility, making it straightforward
to add and handle new cper event types.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Extend ras feature mask to 64-bit for A + A.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a small section dispatch table and record AMD crashdump sections as
RAS_LOG_EVENT_BOOT events. Preserve the original section GUID,
severity, and a bounded copy of the section payload so the existing boot
CPER generator can emit records for debugfs consumers.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add local HEST status and data entry layouts. Also add local helpers for
revision-aware payload access, entry walking, and basic status
validation.
Move the BERT record processing prototype into a dedicated BERT header
so the parser interface stays local to the BERT parser code.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ras_core_get_ras_block_name() indexes ras_block_name[] directly
with enum ras_block_id values. The table only covered entries through
RAS_BLOCK_ID__MPIO, while ras.h defines additional blocks through
RAS_BLOCK_ID__UCIE_PCS.
When UniRAS reports a newer block such as RAS_BLOCK_ID__PCIE_PL,
the lookup falls past the end of the table and returns an empty string.
That leaves messages such as "new correctable hardware errors detected
in block" without the block name.
Fill in the missing names in enum order so the indexed lookup can
resolve PCIE_PL and the other existing ras_block_id values.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a parameter to differentiate callers that need new error
count vs total count, ensuring the new count is only cleared
by the intended caller.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use a common interface to retrieve poison support status
to avoid handling ASIC-specific logic.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The eeprom ras table can be quite large, and each read requires multiple
smu i2c transactions (max 24 bytes per transfer). Limit the validation
to avoid excessive i2c traffic and CPU busy-wait overhead.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use flip-bit mask to generalize bad page address derivation in a row.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add management interface to support psp bad page address translation.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Read and cache the ACPI BERT payload during MCE hardware init, then ask
rascore to process the cached records once for each GPU socket.
Reset the cached state when the MCE notifier chain is torn down so a new
initialization sequence can poll and process boot errors again.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a rascore BERT record walker that validates cached BERT generic
status blocks and iterates their CPER section descriptors.
The generic APEI BERT path may have already consumed the boot error
region and cleared block_status before AMDGPU caches the payload, so do
not use block_status to decide whether cached records should be parsed.
Section-specific parsers can be added separately on top of this walker.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Map boot RAS log events to the boot CPER type so records from
boot-time error sources use the intended CPER record classification.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add the PCIE_PL ACA HWIP mapping for ACA v5 hardware so MCE banks
with HWID 0x1e1 and ACA type 0x0 can be decoded by the RAS ACA path.
Register PCIE_PL as a RAS block using the default ACA bank match and
parse helpers, matching the other simple v5 block mappings.
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Update aca bank decoding for A + A.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The socket ID parsed from ACA IPID always corresponds to the current
socket and never references another socket. Therefore, there is no
need to maintain per-socket storage for remote sockets — a single
socket is sufficient to store all ACA RAS error information for each
GPU device.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
- Adding a new interface in guest driver to parse the pf2vf message and
return RAS capability to the caller when uniras is enabled
- Update RAS capability fields in amdgv_sriovmsg.h for uniras
Signed-off-by: Jiahao Li <Jiahao.Li@amd.com>
Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
